Memory selection circuit for selecting one of various memory areas in a memory unit based on the capacity and the starting address of each area

• US 5,394,538 A
• Filed: 03/23/1994
• Issued: 02/28/1995
• Est. Priority Date: 03/29/1990
• Status: Expired due to Term

• Current Assignee: Sharp Electronics Corporation (Hon Hai Precision Industry Co., Ltd.), Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Wada, Masahiko, Imai, Shigeki
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Asta, Frank J.
• Application Number:
  US08/216,519
• Time in Patent Office: 342 Days
• Field of Search: 395/425, 364/200 MS File, 364/900 MS File, 364/245, 364/245.4, 364/246.7, 364/970
• US Class Current: 711/171
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A memory selection circuit of a computer provided with a central processing unit and a plurality of memory areas of an equal capacity, including the first circuit for storing data corresponding to the capacity of the plurality of memory areas outputted from the central processing unit, the second circuit for storing an address outputted from the central processing unit, the third circuit for generating a signal that indicates a difference between the address stored in the second circuit and a predetermined address assigned to a beginning of the plurality of memory areas; and the fourth circuit for generating a selection signal for selecting one of the plurality of memory areas on the basis of the data stored in the first circuit and the signal generated by the third circuit.

Claims

1. A memory selection circuit of a computer provided with a central processing unit and a memory unit divided into a plurality of memory areas of an equal capacity to be accessed by common lower bits of an address sent from the central processing unit, comprising:

memory capacity storing means for storing capacity data corresponding to said equal capacity of each of said plurality of memory areas, said capacity data being rewritable by signals from the central processing unit;

decoder means for decoding said stored capacity data to generate bit selecting signals;

start address storing means for storing upper bits of a predetermined start address assigned to a beginning of said memory unit, said upper bits being rewritable by signals from central processing unit;

means for comparing bit by bit, upper bits of an address output from said central processing unit and the stored upper bits of said predetermined start address and generating a comparison signal representing a result of each comparison; and

means for generating a selection signal for selecting one of said plurality of memory areas on the basis of the stored capacity data and said comparison signal, said generating means including;

bit selecting means for selecting which address bits to decode based on said bit selection signals,

logic gate means connected to receive said comparison signal and said bit selecting signals for generating a signal representing that the address sent from the central processing unit is in a valid address range starting with said predetermined start address, and

decoding gate means connected to receive said selected address bits and said signal from said logic gate means for decoding said selected address bits to generate said selection signal if the address is in said valid address range.

2. A memory selection circuit as claimed in claim 1, wherein said computer is a microcomputer formed in a single semiconductor chip.

3. A memory selection circuit as claimed in claim 1, wherein all of said memory areas are formed in a single memory element.

4. A memory selection circuit as claimed in claim 1, wherein each of said memory areas is formed in an individual single memory element.

5. A memory selection circuit as claimed in claim 1, wherein each of said memory areas is formed of a plurality of memory elements.

6. A memory selection circuit as claimed in claim 1, wherein said memory capacity storing means includes a plurality of flip-flop circuits connected to receive said data corresponding to said equal capacity of each memory area.

7. A memory selection circuit as claimed in claim 1, wherein said bit selecting means includes a plurality of gates connected to receive said bit selecting signals and address bits to be selected.

8. A memory selection circuit as claimed in claim 7, wherein said plurality of gates are divided into two groups to select adjacent two bits of the address, one group being for one bit and the other group being for the other bit.

9. A memory selection circuit as claimed in claim 1, wherein said comparing means includes a plurality of exclusive OR gates connected to receive said upper bits of the address output from the central processing unit and the data stored in said start address storing means.

10. A memory selection circuit as claimed in claim 9, wherein said logic gate means includes a plurality of gates connected to receive signals from said exclusive OR gates and signals from said decoder means.

11. A memory selection circuit as claimed in claim 10, wherein said logic gate means includes a gate connected to receive signals from said plurality of gates of said logic gate means to generate a signal to be supplied to said decoding gate means if the address is in said valid address range.

12. A memory selection circuit as claimed in claim 1, wherein said start address storing means includes a plurality of flip-flops.