SOI type MOS transistor device

• US 5,395,772 A
• Filed: 03/17/1994
• Issued: 03/07/1995
• Est. Priority Date: 11/23/1990
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Hashimoto, Makoto, Miyazawa, Yoshihiro
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/213,815
• Time in Patent Office: 355 Days
• Field of Search: 357/234, 257/335, 257/336, 257/343, 257/344, 257/347, 437/15, 437/29, 437/30, 437/44, 437/84, 437/913
• US Class Current: 438/163
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

An SOIMOS transistor device which comprises a substrate, an insulating film formed on the substrate, a source and a drain sandwiching a channel region therebetween and formed on the insulating film is described. The channel region has regions in contact with the source and the drain, respectively, and each region has a concentration of an impurity lower than those of the source and the drain, and a gate electrode is formed on the SOI layer. The regions are formed by diffusion of the impurity from the source and the drain in lateral directions, respectively, and extending beneath the gate electrode along the thickness of the source and the drain.

Claims

1. A method for manufacturing a SOI MOS transistor device comprising the steps of:

providing a substrate;

forming an insulating film on a surface of said substrate;

forming an SOI layer which has a thickness of 0.1 μ

m or less on said insulating film;

forming a gate insulating film on a portion of said SOI layer;

first ion implanting an n-type low concentration impurity into said SOI layer, using said gate electrode as a mask, to form a source region and a drain region;

applying a thermal treatment to said device to form a lightly-doped source region and a lightly-doped drain region by side diffusion of said n-type low concentration impurity in said course region and said drain region, under the opposite side edges of said gate electrode, said lightly doped source region and said light-doped drain region disposed below and under the side edges of said gate electrode; and

second ion implanting an n-type high concentration impurity into said SOI layer using said gate electrode as a mask to form said source region and said drain region.

2. A method for manufacturing a SOIMOS transistor device comprising the steps of:

forming an SOI layer which has a thickness of 0.1 μ

m or less on a substrate;

forming a gate electrode over a portion of said SOI layer;

first implanting a low concentration impurity of a first type into said SOI layer using said gate electrode as a mask to form a source region, a drain region and a channel region, said channel region disposed below said portion of said SOI layer over which said gate electrode is formed;

applying a thermal treatment to said device to produce a low concentration impurity of said first type source region and a low concentration impurity of said first type drain region, said low concentration impurity source region disposed under the side edge of said gate electrode between said channel region and said source region, and said low concentration impurity drain region disposed under the side edge of said gate electrode between said channel region and said drain region; and

second implanting said SOI layer with a high concentration impurity of said first type using said gate electrode as a mask so as to increase the first type of impurity concentration in and form said source and drain regions.