Thin film transistor device having driving circuit and matrix circuit

• US 5,396,084 A
• Filed: 06/02/1993
• Issued: 03/07/1995
• Est. Priority Date: 06/03/1992
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Casio Computer Company Limited
• Inventors: Matsumoto, Hiroshi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/070,724
• Time in Patent Office: 643 Days
• Field of Search: 257/57, 257/59, 257/66, 257/72, 257/347, 257/350, 257/351, 257/411, 257/202
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A thin film semiconductor device comprises a matrix circuit portion and a peripheral circuit portion. An NMOS thin film transistor included in the peripheral circuit portion comprises as an active layer a polysilicon thin film formed on a substrate, leading to a high on-current and an improved switching speed, compared with a thin film transistor including as an active layer of a polysilicon thin film which is obtained by crystallizing an amorphous silicon thin film. An NMOS thin film transistor included in the matrix circuit portion also comprises as an active layer a polysilicon thin film which is formed on the substrate. However, the gate insulating film of an NMOS thin film transistor in the matrix circuit portion as a whole is made thicker than that in the NMOS thin film transistor included in the peripheral circuit portion because of the presence of a first interlayer insulating film.

Claims

1. A thin film semiconductor device, comprising:

a substrate having a first region and a second region;

a first non-memory thin film transistor formed on said first region of said substrate and including,

a polysilicon semiconductor thin film,

a gate insulating film, and

a gate electrode, a source electrode and a drain electrode; and

a second non-memory thin film transistor formed on said second region of said substrate and being controllably driven by said first thin film transistor, said second non-memory thin film transistor including,

a polysilicon semiconductor thin film, and

a gate insulating film, a gate electrode, a source electrode and a drain electrode, said gate insulating film of said second thin film transistor being thicker than that of said first thin film transistor;

whereby a gate voltage to reach on-current in said first thin film transistor is lower than that in said second thin film transistor, and a gate voltage range to keep an off-current range in said second thin film transistor is broader than that in said first thin film transistor.

2. The thin film semiconductor device according to claim 1, which further comprises a pixel electrode connected to said source electrode or drain electrode of said second thin film transistor.

3. The thin film semiconductor device according to claim 1, wherein said gate insulating film of said second thin film transistor is of a laminate structure consisting of an upper layer and a lower layer.

4. The thin film semiconductor device according to claim 3, wherein said upper layers of said gate insulating film included in said second thin film transistor covers said gate electrode of said first thin film transistor.

5. A thin film semiconductor device, comprising:

a substrate having a first region and a second region;

a peripheral circuit portion formed on said substrate having a plurality of first non-memory thin film transistors, each of said first thin film transistors including,

a polysilicon semiconductor thin film,

a gate insulating film, and

a gate electrode, a source electrode and a drain electrode; and

a matrix circuit portion formed in the vicinity of said peripheral circuit portion by arranging on said substrate a plurality of second non-memory thin film transistors to form a matrix, each of said second thin film transistors including,

a polysilicon semiconductor thin film,

a gate insulating film, and

a gate electrode, a source electrode and a drain electrode, said gate insulating film included in each of said second thin film transistors being thicker than that included in each of said first thin film transistors, said peripheral circuit portion serving to drive each of said second thin film transistors included in said matrix circuit portion;

whereby a gate voltage to reach on-current in each of said first thin film transistors is lower than that in each of said second thin film transistors, and a gate voltage range to keep an off-current range in each of said second thin film transistors is broader than that in each of said first thin film transistors.

6. The thin film semiconductor device according to claim 5, wherein said substrate is transparent.

7. The thin film semiconductor device according to claim 6, which further comprises a pixel electrode connected to said source or drain electrode of said second thin film transistor and an intermediate electrode.