Vertical DRAM cross point memory cell and fabrication method

• US 5,396,093 A
• Filed: 08/12/1994
• Issued: 03/07/1995
• Est. Priority Date: 02/14/1994
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lu, Chih-Yuan
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/289,741
• Time in Patent Office: 207 Days
• Field of Search: 257/302, 257/306, 257/296, 257/329, 257/330, 257/333, 257/334, 257/303, 257/304, 365/149
• US Class Current: 257/306
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A method is described for making a vertical DRAM cell which includes a vertical channel field effect transistor having a gate electrode and source/drain elements and a capacitor. A pattern of field oxide isolation in a silicon substrate is provided wherein there are a pattern of openings to the silicon substrate. A pattern is formed of buried bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric. The doped polysilicon layer is patterned and etched to form the gate electrode and word lines which are perpendicular to the pattern of buried bit lines. The source/drain elements are formed surrounding the gate electrode in the surface of the substrate by ion implantation using the field oxide and gate electrode and word lines as the mask. The buried bit lines form common and additional source/drain elements. An insulating layer is provided over the pattern of field oxide insulation, word lines and openings to the source/drain elements surrounding the gate electrode. An opening is formed through the insulating layer surrounding the gate electrode. A capacitor is formed in and over the opening through the insulating layer.

Claims

1. A vertical DRAM cell which includes a field effect transistor having a gate electrode, source/drain elements and a capacitor comprising:

providing a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate;

a pattern of buried bit lines and a pattern of lines of holes in the substrate with a hole located within each of said openings to said silicon substrate so that lines of holes and buried bit lines are perpendicular to one another, said lines cross at planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate;

a gate dielectric on surfaces of said holes;

a doped polysilicon layer in and over said holes so that it covers said gate dielectric;

said doped polysilicon layer forms said gate electrode and word lines which are perpendicular to said pattern of buried bit lines;

said source/drain elements surrounding said gate electrode in said substrate;

wherein said buried bit lines form common and additional source/drain elements;

an insulating layer over said pattern of field oxide isolation, said word lines, gate electrode and said source/drain elements surrounding said gate electrode;

an opening through said insulating layer; and

a capacitor in and over said opening through said insulating layer.

2. The vertical DRAM cell of claim 1 wherein the dopant concentration level of said buried bit lines is between about 1 E 19 to 1 E 21 atoms/cm³.

3. The vertical DRAM cell of claim 1 wherein the size of said pattern of openings to said silicon substrate is between about 0.3 to 1.0 micrometers.

4. The vertical DRAM cell of claim 1 wherein said hole located within each of said openings to said silicon substrate is centrally located therein, the hole reaches to said buried bit lines, and has a diameter of between about 0.1 to 0.7 micrometers.

5. The vertical DRAM cell of claim 4 wherein said depth of said hole is between about 0.1 to 0.7 micrometers.

6. The vertical DRAM cell of claim 1 wherein said source/drain elements, said gate electrode in and said additional source/drain elements form said field effect transistor of said vertical DRAM cell.

7. The vertical DRAM cell of claim 6 wherein said capacitor is connected to said field effect transistor to form said vertical DRAM cell.

8. The vertical DRAM cell of claim 1 wherein said capacitor includes a polysilicon node plate in electrical contact with said source/drain elements, a capacitor dielectric layer thereover and a polysilicon ground plate layer over said dielectric layer.

9. A vertical DRAM cell which includes a field effect transistor having a gate electrode, source/drain elements and a capacitor comprising:

providing a base substrate;

a pattern of buried bit lines in said base substrate, and an epitaxial silicon substrate over said base substrate;

a pattern of field oxide isolation in said silicon substrate wherein there are a pattern of openings to the silicon substrate;

a pattern of lines of holes in the substrate with a hole located within each of said openings to said silicon substrate so that lines of holes and said buried bit lines are perpendicular to one another, said lines cross at planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate;

a gate dielectric on surfaces of said holes;

a doped polysilicon layer in and over said holes so that it covers said gate dielectric;

said doped polysilicon layer to form said gate electrode and word lines which are perpendicular to said pattern of buried bit lines;

said source/drain elements surrounding said gate electrode in said substrate;

wherein said buried bit lines form common and additional source/drain elements;

an insulating layer over said pattern of field oxide isolation, said word lines, gate electrode and said source/drain elements surrounding said gate electrode;

an opening through said insulating layer; and

a capacitor in and over said opening through said insulating layer.