Latch controlled output driver
First Claim
1. A latch controlled output driver comprising:
- an output driver circuit including a pull-up transistor and a pull-down transistor connected in series, wherein the pull-up transistor has a first source/drain connected to a first power supply voltage and a second source/drain connected to a first source/drain of the pull-down transistor and the pull-down transistor has a second source/drain connected to a second power supply voltage;
an output point located between the pull-up and pull-down transistors;
a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor;
a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor;
a control circuit connected to the first and second latches, wherein the control circuit may selectively set the first and second latches to first and second preselected states in response to a control signal applied to the control circuit, wherein the pull-up and pull-down transistors are turned off by the first and second latches in the first and second preselected states, wherein the output point is placed into an open state, disabling the latch controlled output driver.
2 Assignments
0 Petitions
Accused Products
Abstract
A latch output driver including an output driver circuit having a pull-up transistor and a pull-down transistor connected in series, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage. The latch controlled output driver also includes a first latch circuit having an output connected to the gate of the pull-up transistor and a second latch circuit having an output connected to the gate of the pull-down transistor. A control circuit is connected to the first and second latches, wherein the control circuit may selectively disable and enable the latch controlled output driver in response to a control signal. A driver output is connected between the pull-up and pull-down transistors, wherein the output driver is in an open state when the latch controlled output driver is disabled by the control circuit. A data circuit is connected to the first and second latch circuits, wherein the data circuit stores the state of the first and second latches present when the latch controlled output driver is enabled and restores the state of the first and second latches when the latch controlled output driver is enabled after being disabled.
26 Citations
26 Claims
-
1. A latch controlled output driver comprising:
-
an output driver circuit including a pull-up transistor and a pull-down transistor connected in series, wherein the pull-up transistor has a first source/drain connected to a first power supply voltage and a second source/drain connected to a first source/drain of the pull-down transistor and the pull-down transistor has a second source/drain connected to a second power supply voltage; an output point located between the pull-up and pull-down transistors; a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor; a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor; a control circuit connected to the first and second latches, wherein the control circuit may selectively set the first and second latches to first and second preselected states in response to a control signal applied to the control circuit, wherein the pull-up and pull-down transistors are turned off by the first and second latches in the first and second preselected states, wherein the output point is placed into an open state, disabling the latch controlled output driver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A latch controlled output driver comprising:
-
an output driver circuit including a pull-up transistor and a pull-down transistor connected in series, wherein the pull-up transistor has a drain connected to a first power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a second power supply voltage; an output connection located between the pull-up and pull-down transistors; a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor; a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor; a first gate having an output connected to the input of the first latch circuit; a second gate having an output connected to the input of the second latch circuit; first and second disable circuits, the first disable circuit being connected to the input of the first latch and the second disable circuit being connected to the input of the second latch, wherein the first and second latches may be set to preselected states such that the pull-up and pull-down transistors are turned off, wherein the latch controlled output driver is disabled; and a data circuit connected to the first and second latches, wherein the data circuit stores data and sends the data to the first and second latches when the latch controlled output driver is enabled after being disabled. - View Dependent Claims (16, 17, 18, 19, 20, 21)
-
-
22. A latch controlled output driver comprising:
-
an output driver circuit including a pull-up transistor and a pull-down transistor, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage; an output connection located between the pull-up and pull-down transistors; a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor; a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor; a first gate having an output connected to the input of the first latch circuit; a second gate having an output connected to the input of the second latch circuit; a first disable transistor having a first source/drain connected to the input of the first latch, a second source/drain connected to the upper power supply voltage, and a gate controlled by a disable signal, wherein said first transistor is turned on by the disable signal; a second disable transistor having a first source/drain connected to the input of the second latch, a second source/drain connected to the upper power supply voltage, and a gate controlled by a disable signal, wherein said first transistor is turned on by the disable signal; a first enable transistor having a first source/drain connected to the input of the first latch and a gate controlled by an enable signal, wherein the transistor is turned on by the enable signal; a second enable transistor having a first source/drain connected to the input of the second latch and a gate controlled by an enable signal, wherein the transistor is turned on by the enable signal; a first data transistor having a first source/drain connected to a second source/drain of the first enable transistor, a second source/drain connected to the lower power supply voltage; a second data transistor having a first source/drain connected to a second source/drain of the second enable transistor, a second source/drain connected to the lower power supply voltage; the latch controlled output driver being disabled when the first and second disabled transistors are turned on and the first and second enable transistors are turned off, wherein the pull-up and pull-down transistors are turned off placing the output connection in an open state disabling the latch controlled output driver; and the latch controlled output driver being enabled when the first and second disabled transistors are turned off and the first and second enable transistors are turned on, wherein the first and second data transistors provide data to the first and second latches enabling the latch controlled output driver. - View Dependent Claims (23, 24, 25, 26)
-
Specification