Polysilicon gate bus with interspersed buffers for driving a row of pixels in an active matrix liquid crystal display

• US 5,396,261 A
• Filed: 03/01/1993
• Issued: 03/07/1995
• Est. Priority Date: 03/01/1993
• Status: Expired due to Fees

• Current Assignee: SpatiaLight, Inc.
• Original Assignee: WAH-III Technology Corp. (SpatiaLight, Inc.)
• Inventors: Hastings, William A. III
• Primary Examiner(s): Weldon, Ulysses
• Assistant Examiner(s): Luu, Matthew
• Application Number:
  US08/022,665
• Time in Patent Office: 736 Days
• Field of Search: 345/87, 345/92, 345/98, 345/99, 359/55, 359/57, 359/59
• US Class Current: 345/92
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A polysilicon gate bus structure used for activating a row of pixels in a matrix of pixels of an active matrix liquid crystal display is described. The polysilicon gate bus is formed with a plurality of buffers interspersed along its length. A plurality of field effect transistors, each associated with one pixel in a row of pixels, have their gate electrodes connected to the polysilicon gate bus with the buffers interspersed among the gate electrode connections so as to speed up a row scanning signal propagation time to each of the gate electrode connections.

Claims

1. A structure for driving four successive pixels in a row of pixels of an active matrix liquid crystal display, comprising:

first, second, third, and fourth field effect transistors formed on a silicon substrate, each field effect transistor having a drain region, a source region, and a gate electrode, wherein said first field effect transistor controls the activation of a first pixel of said four successive pixels, said second field effect transistor controls the activation of a second pixel of said four successive pixels, said third field effect transistor controls the activation of a third pixel of said four successive pixels, and said fourth field effect transistor controls the activation of a fourth pixel of said four successive pixels;

a buffer having a first portion, a second portion, an input, and an output;

a first polysilicon gate bus segment connecting said gate electrodes of said first and second field effect transistors to said input of said buffer; and

a second polysilicon gate bus segment connecting said output of said buffer to said gate electrodes of said third and fourth field effect transistors.

2. The structure as recited in claim 1, said first pixel having a first electrode, said second pixel having a second electrode, said third pixel having a third electrode, and said fourth pixel having a fourth electrode, wherein said first electrode is electrically connected to said source region of said first field effect transistor, said second electrode is electrically connected to said source region of said second field effect transistor, said third electrode is electrically connected to said source region of said third field effect transistor, said fourth electrode is electrically connected to said fourth field effect transistor, and said first electrode is formed over said first and second field effect transistors, said second electrode is substantially formed over said first portion of said buffer, said third electrode is substantially formed over said second portion of said buffer amplifier, and said fourth electrode is formed over said third and fourth field effect transistors.

3. The structure as recited in claim 2, wherein said first portion of said buffer comprises:

a first n-channel field effect transistor having a gate, a source, and a drain; and

a second n-channel field effect transistor having a gate, a source, and a drain;

wherein said gate of said first n-channel field effect transistor is connected to said first polysilicon gate bus segment, said source of said first n-channel field effect transistor is connected to said gate of said second field effect transistor, and said drains of said first and second n-channel field effect transistors are connected to an electrical ground.

4. The structure as recited in claim 3, wherein said second portion of said buffer comprises:

a first p-channel field effect transistor having a gate, a source, and a drain; and

a second p-channel field effect transistor having a gate, a source, and a drain;

wherein said gate of said first p-channel field effect transistor is connected to said gate of said first n-channel field effect transistor of said first portion of said buffer, said drain of said first p-channel field effect transistor is connected to said source of said first n-channel field effect transistor of said first portion of said buffer, said sources of said first and second p-channel field effect transistors are connected to a voltage supply, said gate of said second p-channel field effect transistor is connected to said drain of said first p-channel field effect transistor, and said drain of said second p-channel field effect transistor is connected to said source of said second n-channel field effect transistor of said first portion of said buffer and to said second polysilicon gate bus segment.