Streamlined write operation for EEPROM system

• US 5,396,468 A
• Filed: 11/08/1993
• Issued: 03/07/1995
• Est. Priority Date: 03/15/1991
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Gross, Stephen J., Harari, Eliyahou, Mangan, John S., Mehrotra, Sanjay, Guterman, Daniel C.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): DINH, SON T
• Application Number:
  US08/148,932
• Time in Patent Office: 484 Days
• Field of Search: 365/218, 365/189.01, 365/185
• US Class Current: 365/218
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; and adaptive initial erasing voltages. A streamlined write operation on a flash sector of the EEPROM is implemented by employing the optimized erase in an efficient manner. The write operation includes an initial quick erase of the sector followed by programming of data and verification. Only on those infrequent occasions when a failure occurs as manifested during program verification that the optimized erase will need be evoked.

Claims

1. For an array of electrically erasable and programmable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a transistor that includes a floating gate and an erase electrode, and having a natural threshold voltage that is alterable by programming or erasing to a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein, a method of erasing a sector of addressed cells of the array followed by programming data thereto, comprising the steps of:

reading a set of erase parameters stored in said sector and corresponding thereto;

erasing said sector by employing said set of erase parameters;

programming data including said set of erase parameters into said sector;

verifying the programmed data; and

if the verifying fails, subjecting said sector to an optimized erase comprising;

in a first phase, pulsing said sector with an erase voltage incremented successively from a value derived from said set of erase parameters and verifying a sample of cells of said sector in between pulses until more than a predetermined number of cells in said sector are completely erased; and

thereafter

in a second phase, continuing pulsing said sector with an erase voltage incremented from the last pulsing step and verifying all cells therein in between pulses until they are completely erased; and

repeating the steps of programming and verifying until the verifying passes.

2. The method as in claim 1, wherein said set of erase parameters includes an initial erase voltage, and said step of erasing said sector employing said set of erase parameters includes erasing said sector with a pulse of erase voltage substantially equal to the initial erase voltage.

3. The method as in claim 2, wherein the steps of pulsing and verifying in the first or second phases terminate whenever the erase voltage has incremented beyond a predetermined maximum erase voltage, and thereafter the method further includes subjecting said sector to a defect management process comprising:

providing spare cells in said sector;

replacing incompletely erased cells by mapping to available spare cells if the number of incompletely erased cells does not exceed that of the available spare cells;

otherwise

replacing said sector by mapping to another sector.

4. The method as in claim 2, wherein after the sector fails the verifying of programmed data a second time, the method further includes subjecting said sector to the defect management process, and thereafter, if said sector has not been replaced by another sector, it is subjected to the optimized erase;

otherwise, it is subjected to the step of programming and the step of verifying until the sector is verified.

5. The method as in claim 3, wherein the first phase and second phase pulsing steps apply to all sectors in a cluster thereof, and any sectors that are verified in second phase or are mapped out are removed from said cluster.

6. The method as in claim 2, wherein all erased cells of the sample of cells of said sector are programmed prior to the first pulsing step.

7. The method as in claim 3, wherein all erased cells of the sample of cells of said sector are programmed prior to the first pulsing step.

8. The method as in claim 2, further including the step of:

storing the incremented erase voltage after the number of completely erased cells in the sample exceeds said predetermined number of cells but before a next erase voltage increment, said incremented erase voltage being usable to establish a starting erase voltage for a subsequent erase operation of the same sector.

9. The method as in claim 2, wherein said sector is among a group of selected sectors to be subjected to the method.

10. The method as in claim 9, wherein the step of erasing with a pulse of initial erase voltage further comprises:

determining a minimum value of corresponding initial erase voltages among the group of sectors;

setting an erase voltage substantially equal to the minimum value;

applying a pulse of said erase voltage to all sectors in the group whose initial erase voltages are equal to or greater than said erase voltage;

incrementing said erase voltage by a predetermined amount if there remains any sector in the group that has an initial erase voltage that is greater than said erase voltage; and

repeating the steps of applying, and incrementing until the erase voltage has exceeded the initial erase voltage of all sectors in the group.

11. The method as in claim 9, wherein the step of erasing with a pulse of initial erase voltage further comprises:

determining a minimum value and a maximum value of corresponding initial erase voltages among the group of sectors;

setting an erase voltage substantially equal to the minimum value;

applying a pulse of said erase voltage to all sectors in the group whose initial erase voltages are equal or less than said erase voltage;

incrementing said erase voltage by a predetermined amount if said erase voltage has not exceeded the maximum value; and

repeating the steps of applying, and incrementing until the erase voltage has exceeded the maximum value.