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Streamlined write operation for EEPROM system

  • US 5,396,468 A
  • Filed: 11/08/1993
  • Issued: 03/07/1995
  • Est. Priority Date: 03/15/1991
  • Status: Expired due to Term
First Claim
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1. For an array of electrically erasable and programmable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a transistor that includes a floating gate and an erase electrode, and having a natural threshold voltage that is alterable by programming or erasing to a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein, a method of erasing a sector of addressed cells of the array followed by programming data thereto, comprising the steps of:

  • reading a set of erase parameters stored in said sector and corresponding thereto;

    erasing said sector by employing said set of erase parameters;

    programming data including said set of erase parameters into said sector;

    verifying the programmed data; and

    if the verifying fails, subjecting said sector to an optimized erase comprising;

    in a first phase, pulsing said sector with an erase voltage incremented successively from a value derived from said set of erase parameters and verifying a sample of cells of said sector in between pulses until more than a predetermined number of cells in said sector are completely erased; and

    thereafterin a second phase, continuing pulsing said sector with an erase voltage incremented from the last pulsing step and verifying all cells therein in between pulses until they are completely erased; and

    repeating the steps of programming and verifying until the verifying passes.

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