Bit-line drive circuit for a semiconductor memory

• US 5,398,201 A
• Filed: 04/28/1993
• Issued: 03/14/1995
• Est. Priority Date: 04/05/1989
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd. (Japan Display Incorporated)
• Inventors: Sakurai, Yoshiaki, Kanetani, Kazuo, Nambu, Hiroaki, Ohata, Ken'ichi, Kitsukawa, Goro, Yamaguchi, Kunihiko, Homma, Noriyuki, Higuchi, Hisayuki, Idei, Youji, Odaka, Masanori
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US08/053,330
• Time in Patent Office: 685 Days
• Field of Search: 365/63, 365/177, 365/225.6, 365/190, 365/203
• US Class Current: 365/177
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.

Claims

1. A semiconductor memory comprising:

a plurality of word lines and a plurality of bit line pairs;

memory cells which are coupled to the word lines and the bit line pairs, wherein each memory cell is arranged between respective crosspoints of a word line and a bit line pair and includes a flip-flop comprised of field effect transistors;

first bipolar transistors having bases which are coupled to respective bit lines of the bit line pairs, wherein each said first bipolar transistor outputs information of the memory cell, coupled to the same bit line of the bit line pair to which it is coupled, from its collector in accordance with first and second signals which are inputted to their bases and emitters;

second bipolar transistors having emitters which are coupled to respective bit lines of the bit line pairs, wherein each said second bipolar transistor supplies a charge current to the bit line of the bit line pair to which it is coupled in accordance with third signals which are inputted to their bases; and

third bipolar transistors having collectors which are coupled to respective bit lines of the bit line pairs, wherein each said third bipolar transistor supplies a discharge current to the bit line of said respective bit lines to which it is coupled in accordance with fourth and fifth signals which are inputted to their bases and their emitters,

wherein said third signals have higher (lower) potential levels than said fourth signals, and wherein each third bipolar transistor is a bipolar transistor which supplies a current to the bit line of the respective bit lines to which its collector is coupled only when data is being written into a memory cell coupled between the bit line pair to which the third bipolar transistors are coupled.

2. A semiconductor memory according to claim 1, further including fourth bipolar transistors provided corresponding to said respective bit line pairs,

wherein emitters of the first bipolar transistors coupled to the same bit line pair are commonly coupled to a collector of a fourth bipolar transistor corresponding to the same bit line pair,

wherein current is supplied to one of the first bipolar transistors in accordance with sixth signals which are inputted to bases of the fourth bipolar transistors, and

wherein said sixth signals have lower potential levels than said first signals.

3. A semiconductor memory according to claim 2, wherein one constant current source is coupled to emitters of the fourth transistors and another constant current source is coupled to emitters of respective third bipolar transistors.

4. A semiconductor memory according to claim 1, wherein a constant current source is coupled to each bit line.

5. A semiconductor memory according to claim 1, further comprising capacitors, wherein each capacitor has a first plate coupled to a base of a corresponding second bipolar transistor and a second plate coupled to a constant voltage line.

6. A semiconductor memory according to claim 1, further comprising fifth bipolar transistors, wherein each fifth bipolar transistor has an emitter which is coupled to a base of a corresponding second bipolar transistor and a base which is coupled to a constant voltage line.

7. A semiconductor memory according to claim 1, wherein respective bit line pairs comprise adjacent bit lines which are crossed at a midpoint thereof.

8. A semiconductor memory according to claim 1, further having two constant voltage lines,

wherein said two constant voltage lines are coupled to said memory cells and supply constant voltage thereto, and

wherein at least one of the two constant voltage lines is laid between the bit line pairs coupled to said memory cells.

9. A semiconductor memory according to claim 1, wherein said fourth signal is selected from the group of signals comprising a read/write control signal, a write data signal, and a logical signal resulting from a boolean operation performed on said read/write control signal and said write data signal.

10. A semiconductor memory according to claim 1, wherein said fifth signal is selected from a group of signals comprising a read/write control signal, a write data signal, and a logical signal resulting from a boolean operation performed on said read/write control signal and said write data signal.