Access time speed-up circuit for a semiconductor memory device

• US 5,398,213 A
• Filed: 10/08/1993
• Issued: 03/14/1995
• Est. Priority Date: 10/08/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Young-Ho, Yeon, Eung-Moon
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/133,471
• Time in Patent Office: 522 Days
• Field of Search: 365/238.5, 365/189.05
• US Class Current: 365/238.5
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence

Abstract

A semiconductor memory device includes two latch circuits, each for holding data corresponding to a single normal address. When sequentially used, one after the other, one latch circuit can be storing new data while the other latch circuit outputs its data to the page decoder for subsequent output. Thus, data access delay times for page mode operation are further reduced because the delay which typically results from addressing a normal address is eliminated.

Claims

1. A semiconductor memory device which operates in a page mode comprising:

a memory cell array including a plurality of memory cells, each cell having a normal address, said memory cell array further being divided into a plurality of pages, each page being defined by a page address that represents a plurality of said memory cells;

means for sensing data associated with first and second normal addresses; and

first and second latch circuit arrays for outputting data corresponding to said first normal address when said means for sensing is sensing data corresponding to said second normal address, said first and second latch circuit arrays alternatively activated by a latch control signal generated in response to a change in said normal address.

2. A semiconductor memory device according to claim 1, wherein said device further comprises a page decoder for converting said data generated from said first and second latch circuit arrays into a plurality of data packets, each data packet corresponding to one of said plurality of page addresses, each said data packet consisting of a predetermined number of data bits by said page address.