Packet processing method and apparatus

• US 5,398,245 A
• Filed: 10/04/1991
• Issued: 03/14/1995
• Est. Priority Date: 10/04/1991
• Status: Expired due to Term

• Current Assignee: Avaya Holdings Corporation (Avaya Incorporated)
• Original Assignee: Bay Networks, Inc. (Nortel Networks Corporation)
• Inventors: Harriman, Edward S. Jr.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): TON, DANG T
• Application Number:
  US07/771,769
• Time in Patent Office: 1,257 Days
• Field of Search: 370/94.1, 370/60, 370/60.1, 370/58.1, 370/58.2, 370/58.3, 370/110.1
• US Class Current: 370/389
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2207/3832 Less usual number representations
• CPC Class Codes: G06F 7/38 Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 67/568 Storing data temporarily at an intermediate stage, e.g. caching
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A method and apparatus for processing a data packet, for delivery to a designated location, store selective portions of the packet header in a high speed cache memory to increase processing speed and hence throughput for a packet delivery system. The apparatus and method receive the packets from a data channel source and store portions of the header in cache, and at least the remainder of each data packet is stored in a slower speed memory. A CPU accesses the stored header portion of each packet in cache for necessary protocol and destination information processing of the data packet. The header portions are then overwritten with new data and combined with the remainder of the data packet stored in slower speed memory for transmission to the next packet destination. Preferably, the address at which the remainder portions are stored in slower speed memory determine the cache addresses at which the header portion is stored in high speed cache memory.

Claims

1. A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein said header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of

receiving successive data packets from a data source channel,

storing at least a portion of said header of each data packet in a high speed data cache memory,

storing at least said remainder portion of said each data packet in a slower speed memory,

accessing each header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, and

forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said each data packet.

2. The method of claim 1 further comprising the step of

storing said header of said each data packet at an address identifying the location in said slower speed memory of said remainder portion of said each data packet.

3. The method of claim 1 further comprising the step of

identifying, from an address in said slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored.

4. The method of claim 1 further comprising the steps of

providing plural port access to said high speed data cache memory from at least an input/output data bus and a CPU based processor,

reading said stored header directly from said high speed data cache memory by said processor, and

writing to said high speed data cache memory from said processor for modifying said header.

5. The method of claim 1 further comprising the step of

storing non-adjacent portions of said header in said high speed data cache memory.

6. The method of claim 1 further comprising the step of

selecting portions of said header for storage in said high speed data cache memory depending upon the address in said slower speed memory into which said remainder portion is stored.

7. A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol and including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of

receiving successive data packets from a data source channel,

storing non-contiguous portions of the header of each data packet in a high speed data cache memory,

storing at least said remainder portion of said each data packet in a slower speed memory,

selecting portions of said header of said each data packet for storage in said high speed data cache memory depending upon the address in the slower speed memory into which an associated remainder portion is stored,

identifying, from an address in the slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which the selected portion corresponding to said associated remainder portion is stored,

accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, said accessing step comprising

providing plural port access to said high speed data cache memory from at least an input/output data bus and a CPU based processor,

reading said stored header directly from said high speed data cache memory by said processor, and

writing to said high speed data cache memory from said processor for modifying said header, and

forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of the data packet.

8. An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising

means for receiving successive data packets from a data source channel,

a high speed data cache memory,

a slower speed memory,

means for storing at least a portion of said header of each data packet in said high speed data cache memory,

means for storing at least said remainder portion of said each data packet in said slower speed memory,

means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of the data packet, and

means for forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said data packet.

9. The apparatus of claim 8 further comprising

means for storing each said header portion of a data packet at an address identifying the location in said slower speed memory of the remainder portion of the associated data packet.

10. The apparatus of claim 8 further comprising

means for identifying from an address in said slower speed memory at which each said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored.

11. The apparatus of claim 8 further comprising

means for providing plural port access to said high speed data cache memory from input/output data bus and a CPU based processor,

means for reading said stored header directly from said high speed data cache memory by said processor, and

means for writing to said high speed data cache memory from said processor for modifying said header.

12. The apparatus of claim 8 further comprising

means for storing non-adjacent portions of said header in said high speed data cache memory.

13. The apparatus of claim 8 further comprising

means for selecting portions of said header for storage in said high speed data cache memory depending upon the address in slow memory into which said remainder portion is stored.

14. An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising

means for receiving successive data packets from a data source channel,

a multi-port high speed data cache memory,

means for connecting said high speed data cache memory to an input/output data bus and a CPU based processor,

a slower speed memory,

means for storing non-contiguous portions of said header of each data packet in said high speed data cache memory,

means for storing at least said remainder portion of said each data packet in said slower speed memory,

means for selecting portions of said header for storage in said high speed data cache memory depending upon the address in said slower speed memory into which said remainder portion is stored,

means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said data packet, said accessing means having

means for identifying from an address in said slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored,

means for reading said stored header directly from said high speed data cache memory by said processor, and

means for writing to said high speed data cache memory from said processor for modifying said header, and

means for forwarding a new data packet to a next data packet destination based on the protocol and destination processing of said data packet.