Multi-processor video display apparatus

• US 5,398,315 A
• Filed: 12/30/1992
• Issued: 03/14/1995
• Est. Priority Date: 12/30/1992
• Status: Expired due to Fees

• Current Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Johnson, Brian C., Epstein, Michael A.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US07/998,358
• Time in Patent Office: 804 Days
• Field of Search: 395/101, 395/162, 395/163, 395/164, 358/310, 358/903
• US Class Current: 604/323
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00

Abstract

Video display apparatus having multiple processors for operation in parallel, each processing a respective complete video image in the sequence of video images (fields or frames) which form a video picture, the processing being in accordance with a selected signal processing algorithm. The algorithm may be one which simulates a signal processing circuit design which is to be evaluated, so that the effect of changes in circuit design can be displayed in real time. The signal data for each of the sequential video images is assembled into data packets in successive equal time slots, which are transmitted downstream on a data bus along which are a succession of data processors. The headers of the packets for a given image identify a serially corresponding processor to which such image is assigned, and such packets are processed by the assigned processor in accordance with the selected algorithm. If the processing time of each processor corresponds to the time period of N images, then by using N processors the nth processor will have completed processing of the nth complete image by the time of arrival of the (N+n) th image. Each series of N images can therefor be cyclically assigned to the series of processors, and are processed in parallel in real-time. Provision is made for inter-processor communication when the algorithm has temporal effects on the video picture which necessitate FIR or IIR filtering in order to display such effects.

Claims

1. Video display apparatus for determining the effect of a selected signal processing algorithm on a video picture formed by a video data signal representing time sequential video images which constitute said video picture;

said apparatus comprising;

input interface means for receiving said video data signal and assembling data therein relating to the sequential video images into a train of data packets in successive equal time slots, the data packets including headers identifying to which video image each particular data packet relates;

a data bus having an input for receiving the successive data packets for transmission downstream on said data bus to an output thereof;

a series of a number N (N>

1) of bus latches along said data bus for segmenting said data bus into N successive bus segments, transmission from an upstream bus segment to an adjoining downstream bus segment being controlled by an intervening bus latch;

a series of said number N of programmable bus controllers respectively coupled to the respective bus segments, each bus controller being adapted to control the bus latch for the corresponding bus segment and to determine from the headers of data packets received by said bus latch those of said data packets which relate to a particular video image;

the bus controllers being programmed so that each successive one thereof controls the associated bus latch to select data packets which relate to a corresponding successive image in each series of said number N of sequential video images;

a series of said number N of data processors respectively coupled to the respective bus segments and to the associated bus controllers, each processor receiving from a bus segment coupled thereto data packets selected by the associated bus controller and being programmed to process the received data packets in accordance with said selected signal processing algorithm, the processed data packets being supplied by said processor back to said bus segment for downstream transmission on said data bus as synchronized by said bus controller;

each processor being adapted to complete processing of the data packets relating to a particular video image during a time period corresponding to said number N of successive video images, so that each succeeding series of N successive video images is cyclically assigned by said series of bus controllers to said series of processors and the data packets relating to each series of N video images are processed in parallel; and

output interface means coupled to the output of said data bus to receive the processed data packets relating to successive video images and assemble said processed data packets into a composite output video data signal;

whereby said output video data signal represents time sequential video images corresponding to said video picture as modified by said selected signal processing algorithm.

2. Video display apparatus as claimed in claim 1, further comprising a video display terminal coupled to said output interface means for receiving said output video data, video signal and producing said modified video picture therefrom.

3. Video display apparatus as claimed in claim 1 wherein the selected signal processing algorithm includes processing in the time domain requiring finite impulse response (FIR) filtering, and any nth processor P_n in said series of N processors, where 1<

n<

N, comprises a memory having an input section and an output section and is adapted to;

(i) receive in the input section of the memory of said processor P_n data packets supplied from the output section of the memory of the neighboring upstream processor P_n-1 and which are copies of data packets received by said neighboring upstream processor P_n-1 from the data bus for processing thereby;

(ii) transfer to the output section of the memory of said processor P_n data packets received from said neighboring upstream processor P_n-1, together with copies of data packets received by processor P_n from the data bus for processing thereby; and

(iii) under the control of the bus controller associated with said processor P_n, transfer data packets in the output section of the memory of said processor P_n to the input section of the memory of the neighboring downstream processor P_n+1 ;

whereby each of said processors is supplied with data packets which are to be processed thereby and also with data packets which are to be processed by a neighboring upstream processor.

4. Video display apparatus as claimed in claim 1 wherein the selected signal processing algorithm includes processing in the time domain requiring infinite impulse response (IIR) filtering, and any nth processor P_n in said series of N processors where 1<

n<

N, comprises a memory having an input section and an output section and is adapted to;

(i) receive in the input section of the memory of said processor P_n data packets supplied from the output section of the memory of the neighboring upstream processor P_n-1 and which are copies of processed data packets produced by said neighboring upstream processor P_n-1 ;

(ii) transfer to the output section of the memory of said processor P_n data packets received from said neighboring upstream processor P_n-1, together with copies of processed data packets produced by said processor P_n ; and

(iii) under the control of the bus controller associated with said processor P_n, transfer data packets in the output section of the memory of said processor P_n to the input section of the memory of the neighboring downstream processor P_n+1 ;

whereby each of said processors is supplied with processed data packets produced by a neighboring upstream processor.

5. Video display apparatus as claimed in claim 1, wherein said data bus is in the form of a ring;

said input interface means is a data packet assembler;

said output interface means is a video field assembler; and

said data packet assembler and video field assembler are both comprised in a single interface which includes means for multiplexing both of said assemblers to said data bus.

6. A video display apparatus comprising:

input interface means for receiving a video data signal representing time sequential video images which constitute a video picture and assembling the video data into a succession of data packets for each of the video images;

the data packets being in uniform time slots and having headers identifying to which video image each particular data packet relates;

a data bus having an input coupled to said input interface means to receive successive data packets for downstream transmission on said data bus to an output thereof;

a series of a number N (N>

1) of bus latches along said data bus, each bus latch being controllable to either a latching state or a transmitting state and defining a segment of said data bus which extends to a next adjoining downstream bus latch, thereby forming a series of said number N of successive bus segments;

a series of said number N of programmable bus controllers respectively coupled to said series of N bus segments, each bus controller controlling the upstream bus latch of the relevant bus segment so as to select, based on the headers of data packets on said bus segment, those of said data packets which relate to a video image which is assigned to said bus segment, each series of N successive video images being serially assigned to said series of N successive bus segments;

a series of said number N of data processors respectively coupled to the series of bus segments, each processor receiving from the related bus segment data packets which relate to a video image assigned to said bus segment and being programmed to process said data packets in accordance with a selected video processing algorithm;

the processed data packets produced by a processor being returned by said processor to said bus segment for transmission downstream on said data bus as synchronized by the bus controller for said bus segment;

each data processor being adapted to process data packets relating to a complete video image within a time interval corresponding to N successive video images; and

output interface means for receiving the processed data packets and assembling them into an output video data signal representing said video picture as modified in accordance with said selected video processing algorithm.