Method for data communication

• US 5,398,326 A
• Filed: 02/19/1993
• Issued: 03/14/1995
• Est. Priority Date: 05/15/1989
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Lee, Robert D.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): LANE, JOHN A
• Application Number:
  US08/019,932
• Time in Patent Office: 753 Days
• Field of Search: 395/200, 395/400, 395/425, 235/441, 235/492, 375/7, 364/DIG. 1, 364/DIG. 2, 364/270.5, 364/270.7, 364/271.5, 364/950.1, 364/950.4, 365/189.06, 365/194, 365/221, 257/678, 257/679, 340/825.62, 340/825.06, 340/825.14, 340/825.15
• US Class Current: 711/115
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device
• CPC Class Codes: G06F 3/04897 Special input arrangements or commands for improving display capability
• CPC Class Codes: G06K 19/04 characterised by the shape
• CPC Class Codes: G06K 19/047 the record carrier being shaped as a coin or a gambling token
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 19/0706 the battery being replaceable
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07735 the record carrier comprising means for protecting against electrostatic discharge
• CPC Class Codes: G06K 19/07743 External electrical contacts
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/0021 for reading/sensing record carriers having surface contacts
• CPC Class Codes: G06K 7/0086 the connector comprising a circuit for steering the operations of the card connector
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module'"'"'s battery. A protocol has been specified so that the module never sources current to the data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from a host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read. Thus, the host system, after the falling edge, attempts to pull the data line high again, and then tests the potential of the data line to ascertain the value of the bit read.

Claims

1. A method for data communication by serial block transfers of data on a data line between a first system and at least one second system, said serial block transfers of data having at least one data bit and said data line having at least one voltage state, comprising the steps of:

(a) defining a current operating mode to be either a write mode or a read mode, so that said at least one data bit of said serial block transfers of data is transferred from said first system to said at least one second system when said current operating mode is said write mode and said at least one data bit of said serial block transfers of data is transferred from said at least one second system to said first system when said current operating mode is said read mode;

(b) driving said data line toward a first voltage level by said first system and thereafter driving said data line to make a transition of said data line toward a second voltage;

(c) detecting said transition of said data line toward said second voltage level by said at least one second system;

(d) and when said current operating mode is said read mode,

(d1) driving said data line toward said second voltage level by said at least one second system and holding said data line at said second voltage level for a first time duration, said first time duration having a first length, said first length dependent upon said at least one data bit of said serial block transfers of data and releasing said data line after said first time duration, and

(d2) testing the at least one voltage state of said data line by said first system within a time window, said time window terminates before a minimum possible duration of said first time duration;

(e) and when said current operating mode is said write mode,

(e1) driving said data line toward a data voltage level dependent upon said at least one data bit of said serial block transfers of data said data voltage level approximately equal to said first voltage level or said second voltage level;

(e2) waiting for a second time duration, said second time duration having a second length, said second length dependent upon said at least one data bit of said serial block transfers of data and then testing the at least one voltage state of said data line to ascertain the at least one data bit of said serial block transfers of data written; and

(e3) in said first system, holding said data line to said data voltage level over said time window which begins before an earliest possible expiration, for said at least one second system of said second time duration, and which ends after a latest possible expiration, of said second time duration.

2. The method of claim 1, wherein said serial block transfers of data have a first block transfer, each block of said first block transfer of data having a beginning, and further comprising the additional step of,

at the beginning of the first block transfer of data between said first system and said at least one second system, performing an address-pointer-reset operation, by sending from said first system to said at least one second system, a data sequence which could not possibly occur during said read or write modes.

3. The method of claim 1, wherein said block transfers of data has a beginning, and further comprising the additional step of, at the beginning of each block transfer of data of said block transfers of data between said first system and said at least one second system, transmitting overhead bits from said first system to said at least one second system, to selectably place said at least one second system in said read mode or in said write mode.

4. The method of claim 1, wherein said first time duration is substantially equal to said second time duration.

5. The method of claim 1, wherein said first voltage corresponds to a logical high and is approximately 5 volts and said second voltage corresponds to a logical low and is approximately 0 volts.

6. The method of claim 1, wherein said first time duration and said second time duration is at least one microsecond.

7. The method of claim 1, wherein said time window is at least 30 microseconds from said transition.

8. The method of claim 1, wherein said second system is a button-shaped electronic token.

9. The method of claim 1, wherein said first system and said at least one second system is an integrated circuit.

10. The method of claim 1, wherein said testing that occurs in both read and write modes is performed for each data bit(s) of said data, so that data bit(s) are read or written bit by bit.

11. The method of claim 1, wherein after said driving said data line toward a first voltage level by said first system and before driving said data line to make a transition of said data line toward a second voltage, comprising the following step of

holding said data line for a first time period that is long enough to ensure that an edge detector in said second system will have sufficient set-up time.

12. The method of claim 1, wherein said second voltage level is approximately ground and corresponds to a logic low level.

13. The method of claim 1, wherein said transition provides a coordinating time from which said second system coordinates internal operations.

14. The method of claim 1, wherein said first time length is at least one microsecond.

15. The method of claim 1, wherein said second time length is at least one microsecond.

16. The method of claim 1, further comprising the following steps:

(f) repeating steps (a) through (e).

17. The method of claim 1, wherein said time window is at least 30 microseconds from said transition.

18. The method of claim 1, wherein said data bit is selected from the group consisting of a logical one value and a logical zero value.

19. The method of claim 1, wherein said first length of said first time duration and said second length of said second time duration when combined together do not exceed 60 microseconds from said transition.

20. The method of claim 1, wherein said first length of said first duration and said second length of said second duration when combined together create a fourth time duration having a fourth length which is approximately four times said second length of said second time duration.

21. The method of claim 1, wherein said first system performs steps (a), (b), and (c).

22. The method of claim 1, wherein said at least one second system performs step (d).

23. The method of claim 1, wherein said transition is a falling edge.

24. The method of claim 1, wherein said transition has a corresponding transition time and a corresponding transition rate, said corresponding transition time and said corresponding transition rate vary with temperature.

25. The method of claim 1, wherein said first voltage level is approximately five volts and corresponds to a logic high level.