Method and apparatus for performing wafer level testing of integrated circuit dice

• US 5,399,505 A
• Filed: 07/23/1993
• Issued: 03/21/1995
• Est. Priority Date: 07/23/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Cheng, Shih K., Carlquist, James H., Yarbrough, Thomas R., Ballouli, Walid S., Long, Kenneth J., Dasse, Edward C., Bollish, Robert W., Toewe, Charles F., Figueroa, Alfredo, Burton, Marcus R., Holub, Kelvin L.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/096,094
• Time in Patent Office: 606 Days
• Field of Search: 437/8, 437/226, 437/227, 324/158 R, 324/158 T
• US Class Current: 438/17
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

Claims

1. A method for providing a semiconductor substrate comprising at least one tested integrated circuit data processor, the method comprising the steps of:

providing the semiconductor substrate having at least one integrated circuit data processor formed thereon, the at least one integrated circuit data processor having a top surface;

forming a first conductor overlying the top surface of the at least one integrated circuit data processor, such that the first conductor is electrically coupled to the at least one integrated circuit data processor;

supplying a clock signal to the integrated circuit data processor by way of the first conductor;

performing a functional test of the at least one integrated circuit data processor by executing a plurality of data processor instructions;

using the clock signal in carrying out execution of the plurality of data processor instructions; and

removing at least a portion of the first conductor from the top surface of the at least one integrated circuit data processor.

2. A method as in claim 1, wherein the functional test is a full functional test.

3. A method as in claim 2, wherein said step of performing a functional test comprises the step of:

executing a built in self test.

4. A method as in claim 1, wherein the functional test is a burn-in test.

5. A method as in claim 1, wherein said step of performing a functional test comprises the steps of:

supplying a data signal to the plurality of integrated circuit data processors by way of a second conductor;

supplying a first voltage level to the plurality of integrated circuit data processors by way of a third conductor;

supplying a second voltage level to the plurality of integrated circuit data processors by way of a fourth conductor; and

supplying a reset signal to the plurality of integrated circuit data processors by way of a fifth conductor.

6. A method as in claim 5, wherein said step of performing a functional test further comprises the steps of:

supplying a third voltage level to the plurality of integrated circuit data processors by way of a sixth conductor;

storing test result information in the at least one integrated circuit data processor, the test result information indicating if the at least one integrated circuit data processor failed the functional test;

transferring the test result information from the at least one integrated circuit data processor to a data collection system; and

differentiating each of the plurality of integrated circuit data processors such that each of the plurality of integrated circuit data processors can be uniquely identified.

7. A method as in claim 1, further comprising the step of:

storing test result information in the at least one integrated circuit data processor, the test result information indicating if the at least one integrated circuit data processor failed the functional test.

8. A method as in claim 1, further comprising the step of:

transferring the test result information from the at least one integrated circuit data processor to a data collection system.

9. A method as in claim 1, wherein the at least one integrated circuit data processor is a plurality of integrated circuit data processors.

10. A method as in claim 9, further comprising the step of:

differentiating each of the plurality of integrated circuit data processors such that each of the plurality of integrated circuit data processors can be uniquely identified.

11. A method as in claim 10, wherein said step of differentiating each of the plurality of integrated circuit data processors comprises the step of:

providing each of the plurality of integrated circuit data processors with a code that indicates a unique location on the semiconductor substrate.

12. A method as in claim 9, wherein said step of performing a functional test comprises the step of:

supplying a data signal to the plurality of integrated circuit data processors by way of a second conductor.

13. A method as in claim 12 wherein said step of performing a functional test further comprises the steps of:

supplying a first voltage level to the plurality of integrated circuit data processors by way of a third conductor; and

supplying a second voltage level to the plurality of integrated circuit data processors by way of a fourth conductor.

14. A method as in claim 13, wherein said step of performing a functional test further comprises the step of:

supplying a third voltage level to the plurality of integrated circuit data processors by way of a fifth conductor.

15. A method as in claim 14, wherein said step of performing a functional test further comprises the step of:

supplying a reset signal to the plurality of integrated circuit data processors by way of a sixth conductor.

16. A method as in claim 1, wherein said step of forming comprises the step of:

depositing a metal layer,

17. A method as in claim 16, wherein said step of removing comprises the step of:

etching the metal layer.

18. A method as in claim 17, wherein said step of removing further comprises the step of:

protecting a plurality of bonding pads with an insulating layer.

19. A method as in claim 1, wherein said step of performing a functional test comprises the steps of:

placing the semiconductor substrate in a test fixture having an edge connector; and

electrically coupling a plurality of wafer contact pads to the edge connector, said plurality of wafer contact pads being formed on the semiconductor substrate.

20. A method as in claim 19, wherein said step of electrically coupling comprises the step of:

placing a plurality of pogo pins such that each pogo pin is in physical contact with one of the plurality of wafer contact pads.

21. A method of fabricating and testing a plurality of integrated circuits comprising the steps of:

fabricating a plurality of integrated circuits on a first major surface of a semiconductor wafer, each of the integrated circuits having a plurality of connection points suited for making electrical contacts to each of the integrated circuits, the first major surface of the semiconductor wafer also including dicing lanes separating individual ones of the plurality of integrated circuits and a peripheral region adjacent to an edge of the semiconductor wafer;

forming a layer of insulating material overlying the first major surface of the semiconductor wafer;

patterning the layer of insulating material to open contact vias overlying a portion of the plurality of connection points on each of the plurality of integrated circuits;

forming a plurality of conductors on a surface of the layer of insulating material, each of the plurality of conductors extends into at least one of the contact vias overlying each of the plurality of integrated circuits, each of the plurality of conductors extends into the peripheral region of the semiconductor wafer and a portion of at least one of the plurality of conductors overlies at least one of the plurality of integrated circuits;

establishing electrical contact in the peripheral region of the semiconductor wafer between each of the plurality of conductors and an integrated circuit tester apparatus;

operating the integrated circuit tester apparatus to test each of the plurality of integrated circuits using the plurality of conductors;

producing a test result in response to said step of operating the integrated circuit tester apparatus;

differentiating each of the plurality of integrated circuits such that each of the plurality of integrated circuits can be uniquely identified; and

transferring the test result from each of the plurality of integrated circuits to the integrated circuit tester apparatus.

22. A method for providing a semiconductor substrate comprising a plurality of tested integrated circuits, the method comprising the steps of:

providing the semiconductor substrate having integrated circuits formed thereon, a total number of the integrated circuits being N integrated circuits, the N integrated circuits being separated by a first set of parallel dicing lanes and a second set of parallel dicing lanes, where the first set of parallel dicing lanes are perpedicular to the second set of parallel dicing lanes;

forming a first wafer conductor overlying the semiconductor substrate, the first wafer conductor being electrically coupled to the N integrated circuits, the first wafer conductor having a first set of conductor portions which are parallel to the first set of parallel dicing lanes, the first wafer conductor having a second set of conductor portions which are parallel to the second set of parallel dicing lanes; and

performing a functional test of the N integrated circuits using the first wafer conductor; and

wherein the first set of conductor portions of the first wafer conductor overlies a first area of the semiconductor substrate such that more than half of the first area of the semiconductor substrate has integrated circuits formed thereon.

23. A method as in claim 22, further comprising the step of:

forming a plurality of current limiting elements, each current limiting element having a first terminal coupled to the first wafer conductor and having a second terminal coupled to a corresponding one of the N integrated circuits.

24. A method as in claim 22, further comprising the step of:

forming a wafer contact pad on a periphery of the semiconductor substrate such that the first wafer contact pad is electrically coupled to the first wafer conductor.

25. A method as in claim, 24, wherein said step of forming a first wafer conductor and said step of forming a wafer contact pad are performed concurrently.

26. A method as in claim 22, further comprising the step of:

forming a second wafer conductor overlying the semiconductor substrate, the second wafer conductor being electrically coupled to the N integrated circuits, the second wafer conductor having a first set of conductor portions which are parallel to the first set of parallel dicing lanes, the second wafer conductor having a second set of conductor portions which are parallel to the second set of parallel dicing lanes;

wherein the first set of conductor portions of the second wafer conductor overlies a second area of the semiconductor substrate such that more than half of the second area of the semiconductor substrate has the first set of parallel dicing lanes formed thereon.

27. A method as in claim 26, wherein said step of forming a first wafer conductor and said step of forming a second wafer conductor are performed concurrently.

28. A method as in claim 26, further comprising the steps of:

forming a first plurality of wafer contact pads on a periphery of the semiconductor substrate such that the first plurality of wafer contact pads is electrically coupled to the first wafer conductor; and

forming a second plurality of wafer contact pads on the periphery of the semiconductor substrate such that the second plurality of wafer contact pads is electrically coupled to the second wafer conductor.

29. A method as in claim 28, wherein said steps of forming a first wafer conductor, forming a second wafer conductor, forming a first plurality of wafer contact pads, and forming a second plurality of wafer contact pads are performed concurrently.

30. A method as in claim 22, wherein said step of providing the semiconductor substrate comprises the steps of:

forming a plurality of bonding pad contacts on each of the N integrated circuits; and

forming a plurality of mini-pad contacts on each of the N integrated circuits, such that each of the plurality of mini-pad contacts is associated with a corresponding one of the plurality of bonding pad contacts.

31. A method as in claim 30, further comprising the step of:

forming a plurality of current limiting elements, each current limiting element having a first terminal coupled to the first wafer conductor and having a second terminal coupled to a corresponding one of the mini-pad contacts.

32. A method for providing a semiconductor substrate comprising a plurality of tested integrated circuits, the method comprising the steps of:

providing the semiconductor substrate having a plurality of integrated circuits formed thereon, the plurality of integrated circuits being arranged in a plurality of rows and a plurality of columns, each of the plurality of integrated circuits having a length and a width, the plurality of integrated circuits being separated by a first set of parallel dicing lanes and a second set of parallel dicing lanes, where the first set of parallel dicing lanes are perpedicular to the second set of parallel dicing lanes;

forming a first wafer conductor overlying the semiconductor substrate, the first wafer conductor being electrically coupled to the plurality of integrated circuits, the first wafer conductor having a first set of conductor portions which are parallel to the first set of parallel dicing lanes, the first wafer conductor having a second set of conductor portions which are parallel to the second set of parallel dicing lanes, a one of the first set of conductor portions overlying one of the length and width of one of the plurality of integrated circuits; and

performing a functional test of the plurality of integrated circuits using the first wafer conductor.

33. A method as in claim 32, wherein the plurality of integrated circuits are a total number of integrated circuits formed on the semiconductor substrate.