Device for the 3D encapsulation of semiconductor chips
First Claim
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1. A device for the encapsulation of semiconductor chips comprising a plurality of chips, each of said chips comprising connection pads;
- connection means for each of the chips, said connection means comprising an insulating film and conductive tracks positioned on said film, said tracks being connected to the pads by means of conductors, said tracks and conductors making electrical connections extending from the pads of the chips towards at most three of four sides of the chips, the chips with the connection means being fixedly joined to each other by means of an electrically insulating material to form a stack, so that the conductors are flush with the faces of the stack except on at least the face which is located on the fourth side of the chips, electrical connection of the conductors to one another being achieved by connections on the faces of the stack.
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Abstract
Disclosed is a 3D encapsulation of semiconductor chips, each chip containing for example an integrated circuit, this encapsulation being aimed at optimising heat dissipation by conduction. Connection means are associated with each chip, making it possible to extend the pads of chips towards three sides of the chip, thus leaving the fourth side free. The chips are stacked on one another and then can be connected to heat dissipation means by their fourth side.
73 Citations
18 Claims
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1. A device for the encapsulation of semiconductor chips comprising a plurality of chips, each of said chips comprising connection pads;
- connection means for each of the chips, said connection means comprising an insulating film and conductive tracks positioned on said film, said tracks being connected to the pads by means of conductors, said tracks and conductors making electrical connections extending from the pads of the chips towards at most three of four sides of the chips, the chips with the connection means being fixedly joined to each other by means of an electrically insulating material to form a stack, so that the conductors are flush with the faces of the stack except on at least the face which is located on the fourth side of the chips, electrical connection of the conductors to one another being achieved by connections on the faces of the stack.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor stack comprising:
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(a) a plurality of semiconductor chips each having two major faces and four side faces, a plurality of connection pads distributed on one major face near a periphery of said face close to four sides of said chip, said chip being positioned with the major faces parallel to each other; (b) a plurality of first conductors extending from the pads on three of said peripherals outward from said chips and substantially parallel to said major faces; (c) a plurality of central frames of dielectric material, one for each of said chips, and having a plurality of electrically conductive tracks thereon, each of said frames being positioned adjacent to one of said chips, each track having one end near said fourth side of said chip and the other end near one of the three other sides; (d) a plurality of electrical connections extending between the pads on the fourth of said peripheries of said chips to said one end of said electrically conductive tracks; (e) a plurality of second conductors extending from said other end of said tracks outward from said chips and frames and substantially parallel to said major surfaces; (f) an insulating material between said chips and bonding said chips, frames, and conductors into a single stack with the conductors extending to three surfaces of said stack which correspond to said three sides of said chips. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification