Semiconductor device allowing accurate characteristics test

• US 5,400,290 A
• Filed: 10/26/1993
• Issued: 03/21/1995
• Est. Priority Date: 10/29/1992
• Status: Expired due to Term

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tsukude, Masaki, Adachi, Yukinobu, Suma, Katsuhiro
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/141,002
• Time in Patent Office: 511 Days
• Field of Search: 365/226, 365/227, 365/233, 365/191, 365/193, 365/201
• US Class Current: 365/226
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

In response to an external control signal, a first timing detecting circuit and a high voltage detecting circuit detect setting of a signature mode and provide a signature mode signal to a second timing detecting circuit. The second timing detecting circuit outputs an output buffer activating signal to the output buffer in response to the external control signal. In response to the output buffer activating signal, the output buffer detects an internal supply voltage and provides the same to an external pin.

Claims

1. A semiconductor device on a chip providing a potential at a prescribed internal node to an external terminal of said chip in a prescribed mode, comprising:

a first designating signal output means responsive to a first external control signal from off said chip outputting a first designating signal designating said prescribed mode;

a second designating signal output means responsive to a second external control signal from off said chip and to said first designating signal for outputting a second designating signal to activate a connection to said external terminal; and

output means responsive to said second designating signal for connecting the potential of said prescribed internal node to said external terminal of said chip.

2. The semiconductor device according to claim 1, wherein

said first external control signal includes a high potential signal having a potential higher than a normally input high potential;

and

said first designating signal output means includes high voltage detecting means responsive to said high potential signal for outputting a high potential detecting signal, and

timing detecting means responsive to said first external control signal except said high potential signal and to said high potential detecting signal for outputting said first designating signal.

3. The semiconductor device according to claim 2, wherein

said semiconductor device is a dynamic random access memory;

said first external control signal includes a row address strobe signal, a column address strobe signal, a write enable signal and an address signal; and

said high potential signal is the address signal.

4. The semiconductor device according to claim 3, wherein

when said write enable signal and said column address strobe signal which are at an active state are input, said row address strobe signal which is at the active state is input thereafter and said high voltage detecting signal which is at the active state is input,

said first timing detecting circuit sets said first designating signal in response to a timing of change of said row address strobe signal from the active state to an inactive state.

5. The semiconductor device according to claim 3, wherein

said write enable signal and said column address strobe signal are at an inactive state,

said first timing detecting circuit resets said first designating signal in response to a timing of change of said row address strobe signal from an active state to the inactive state.

6. The semiconductor device according to claim 3, when said write enable signal is at an inactive state and said column address strobe signal which is at an active state is input,

said first timing detecting circuit resets said first designating signal in response to a timing of change of the row address strobe signal from the active state to the inactive state.

7. The semiconductor device according to claim 1, wherein

said second external control signal is different from a signal which changes state of said first designating signal.

8. The semiconductor device according to claim 7, wherein

said semiconductor device is a dynamic random access memory, and

said second external control signal includes a row address strobe signal, a column address strobe signal and a write enable signal.

9. The semiconductor device according to claim 1, wherein

said first designating signal output means includes

counting operation control means responsive to said first external control signal for outputting a counting operation control signal for controlling counting operation, and

counting means responsive to said counting operation control signal for counting change of status of said first external control signal and for outputting said first designating signal when the counted values reaches a prescribed value.

10. The semiconductor device according to claim 9, wherein

said semiconductor device is a dynamic random access memory, and

said first external control signal includes a row address strobe signal, a column address strobe signal, and a write enable signal.

11. The semiconductor device according to claim 10, wherein

said counting operation control means provides, after said write enable signal and said column address strobe signal which are at an active state are input, a counting operation starting signal for designating start of counting operation to said counting means in response to a timing of change of said row address strobe signal from an inactive state to the active state, and

said counting means counts the change of status of said column address strobe signal in response to said counting operation starting signal.

12. The semiconductor device according to claim 10, wherein

said counting operation control means provides, when said column address strobe signal is at the active state and said write enable signal is at the inactive state, a reset signal for designating resetting of said first designating signal to said counting means in response to a timing of change of said row address strobe signal from the inactive state to the active state, and

said counting means resets said first designating signal in response to said reset signal.

13. The semiconductor device according to claim 1, wherein

said second designating signal output means further includes

selecting means for selecting said prescribed internal node based on a third external control signal for selecting said prescribed internal node, and output a third designating signal designating output of the potential of the internal node selected by said selecting means;

and

said output means outputs the potential of said selected prescribed internal node to said external terminal in response to said second and third designating signals.

14. The semiconductor device according to claim 1, wherein

said first external control signal includes a plurality of high potential signals having higher potential than a normally input high potential,

said high potential signals being selecting signals for selecting said prescribed internal node;

said first designating signal output means includes

a plurality of high potential detecting means responsive to said plurality of high potential signals for outputting a plurality of first high potential detecting signals,

second high potential detecting means responsive to said plurality of first high potential detecting signals for outputting a second high potential detecting signal, and

first timing detecting means responsive to said first external control signal except said high potential signal and to said second high potential detecting signal for outputting said first designating signal;

said second designating Signal output means includes

second timing detecting means responsive to said first designating signal and to said second external control signal for outputting a potential output designating signal designating output of the potential of the internal node,

internal node selecting means responsive to said first high potential detecting signal for outputting an internal node selecting signal selecting said prescribed internal node, and

selecting means responsive to said potential output designating signal and said internal node selecting signal for outputting a plurality of second designating signals for designating output of the potential of the internal node selected by said internal node selecting means; and

said output means includes

a plurality of potential output means responsive to said plurality of second designating signal for outputting potential of the designated internal node.

15. The semiconductor device according to claim 14, wherein

said semiconductor device is a dynamic random access memory;

said first external control signal includes a row address strobe signal, a column address strobe signal, a write enable signal and an address signal;

said high potential signal includes an address signal; and

said second external control signal includes a row address strobe signal, a column address strobe signal and a write enable signal.

16. The semiconductor device according to claim 1, wherein

said first external control signal includes a high potential signal which has a potential higher than a normally input high potential;

said first designating signal output means includes detecting operation control means responsive to said first external control signal except said high potential signal for outputting a detecting operation control signal for controlling high potential detecting operation,

high potential detecting means responsive to said detecting operation control signal and said high potential signal for outputting a high potential detecting signal, and

a timing detecting circuit responsive to said first external control signal except said high potential signal and to said high potential detecting signal for outputting said first designating signal;

said high potential detecting means includes

voltage lowering means for converting said high potential signal to a signal of a second potential by lowering the voltage by a first voltage,

detecting means for outputting, when the potential of said signal of the second potential is higher than a third potential, said high potential detecting signal, and

adjusting means for adjusting said first voltage or third potential.

20. The semiconductor device according to claim 1, wherein the potential of said prescribed internal node is generated by:

lowered voltage generating means for lowering an externally supplied voltage.

17. A semiconductor device on a chip, comprising:

voltage lowering means for converting an external input signal having a first potential to a signal having a third potential by lowering the potential by a second potential;

detecting means for outputting, when the potential of said signal of the third potential is higher than a fourth potential, a prescribed first potential detecting signal; and

adjusting means for adjusting one of said second potential or said fourth potential in response to an external control signal from off said chip.

18. The semiconductor device according to claim 17, wherein

said voltage lowering means receives said external input signal of the first potential and includes a first n type transistor group including a plurality of diode connected n type transistors connected in series;

said detecting means includes

first boosted voltage generating means responsive to a control signal for outputting a first boosted signal of a boosted potential,

a first n type transistor connected to said first n type transistor group and receiving at its gate said first boosted signal, and

a second n type transistor connected between said first n type transistor and a ground potential and receiving at its gate a supply voltage IV_CC ;

said adjusting means for adjusting said second voltage includes

second boosted voltage generating means responsive to an adjusting signal for adjusting said second voltage for outputting a second boosted signal of a boosted potential, and

a second n type transistor group connected parallel to a part of said first n type transistor group and receiving at its gate said second boosted signal.

19. The semiconductor device according to claim 17, wherein

said voltage lowering means receives said external input signal of the first potential and includes a first n type transistor group including a plurality of diode connected n type transistors connected in series;

said detecting means includes

first boosted voltage generating means responsive to a control signal for outputting a first boosted signal of a boosted potential,

a first n type transistor connected to said first n type transistor group and receiving at its gate said first boosted signal,

a p type transistor connected to a supply voltage and receiving at its gate the ground potential,

a second n type transistor group connected to said p type transistor and including a plurality of diode connected n type transistors connected in series, and

a second n type transistor connected between said first n type transistor and the ground potential and receiving at its gate an output from a contact node between said p type transistor and said second n type transistor group; and

said adjusting means for adjusting the fourth potential includes

a third n type transistor connected parallel to a part of said second n type transistor group and receiving at its gate an adjusting signal for adjusting said fourth potential.