Apparatus and method for defective column detection for semiconductor memories

• US 5,400,343 A
• Filed: 02/28/1992
• Issued: 03/21/1995
• Est. Priority Date: 02/28/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Minemier, Ronald K., Crittenden, Brent S.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Snyder, Glenn
• Application Number:
  US07/843,525
• Time in Patent Office: 1,117 Days
• Field of Search: 371/21.4, 371/21.1, 365/201
• US Class Current: 714/721
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A circuit and method are provided for a pad efficient and speed efficient test of column leakage currents in silicon memory devices. Memory circuits are blocked into memory bit planes associated with individual I/O pins. Adequate testing requires that each column in each bit plane be tested for charge leakage characteristics. Rather than switching between I/O pins to test memory blocks associated with given pins, the switching circuitry is implemented on the silicon and is selectively coupled to the outputs of the bit planes on the chip. A single high voltage analog output pin is provided for test observations. This eliminates the need to ramp the testing system'"'"'s voltages up and down and avoids the problems of hot switching between I/O pins.

Claims

1. A non-volatile semiconductor memory fabricated on a silicon substrate and employing a plurality of non-volatile memory cells arranged in an array of rows and columns wherein each column is associated with one of a plurality of bit planes, each of said bit planes having an analog line selectively coupled to the columns making up a given bit plane, said non-volatile semiconductor memory being capable of receiving an applied test voltage across all of said rows, an improvement for verifying column leakage characteristics comprising:

an analog multiplexer fabricated on said substrate and coupled to receive as input signals each of the analog lines from each of said plurality of bit planes, said analog multiplexer further being coupled to receive control signals for selecting which of said analog input signals to output, said analog multiplexer providing an analog output signal such that a current measuring device coupled to said analog output signal measures leakage current from a selected column if said selected column is subject to current leakage.

2. The improvement of claim 1 further comprising a high-voltage output pad coupled to said analog multiplexer for receiving the selected output from said analog multiplexer and providing an observation point for said current measuring device to measure for charge leakage characteristics.

3. The improvement of claim 1 wherein said analog multiplexers means comprises:

an analog output signal line selectively coupled to the analog lines of said plurality of bit planes; and

a plurality of switching transistors coupled between said analog output signal line and said plurality of bit planes for selecting which bit planes output will be passed to said analog output signal line.

4. A method of screening an integrated circuit for memory column charge leakage characteristics, said integrated circuit having an array of rows and columns of non-volatile memory cells, said method comprising the steps of:

applying a potential to the rows of said array of non-volatile memory cells;

selectively coupling at least one of said columns of said array of non-volatile memory cells through a silicon implemented analog multiplexer to an output pad on said integrated circuit; and

measuring the output current at said output pad to determine if a selected column exhibits charge leakage characteristics by having a current above an allowable threshold.

5. The method of claim 4 further comprising the step of iteratively repeating said steps for screening said integrated circuit for memory column charge leakage until every column of said array of memory cells has been measured for charge leakage characteristics.

6. A method for stressing a non-volatile memory array, having a plurality of rows and columns on an integrated circuit comprising the steps of:

applying a potential substantially greater than the operating voltage of the integrated circuit to a high-voltage capable pad of the integrated circuit;

selectively coupling electrically said pad through an on-chip analog multiplexer to the desired columns of said non-volatile memory array; and

holding said potential across said desired columns of said non-volatile memory array for a predetermined period of time, thereby stressing said non-volatile memory array.