Semiconductor device having a basic cell region and an I/O cell region defined on a surface thereof

• US 5,401,989 A
• Filed: 07/06/1993
• Issued: 03/28/1995
• Est. Priority Date: 07/06/1992
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kikuchi, Kazunori
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): GUAY, JOHN FRANCIS
• Application Number:
  US08/086,299
• Time in Patent Office: 630 Days
• Field of Search: 257/202, 257/203, 257/207, 257/208, 257/210, 257/211, 257/528, 257/532, 257/533, 257/536
• US Class Current: 257/211
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures

Abstract

A signal line is disposed to run parallel to electric-power supplying lines in the uppermost layer of a multi-layer wiring in an ASCI (Application-oriented Specific IC). An arbitrary cell in an I/O cell column can be interconnected to a large-size circuit element, such as a feedback resistor, formed at a corner of a semiconductor chip. Therefore, a desired function circuit block can be formed in an I/O cell corresponding to an arbitrary input/output pin so that satisfactory freedom is assured for a user who design the pattern on a printed circuit board. Since the signal line is formed by an individual conductive layer from that for the signal line and as well as it runs adjacently to the electric-power line, inductive coupling with other signal lines can significantly be reduced. As a result, a stable operation of an oscillation circuit constituted by the feedback resistor and a selected internal I/O cell can be assured. According to the present invention, the necessity of an additional conductive layer to be formed in the multi-layer wiring can be eliminated. Therefore, increase in the number of manufacturing processes and the overall cost can, of course, be prevented.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a basic cell region defined at the central area of a surface thereof;

an array of input-output circuit cells arranged along an edge of the surface outside the basic cell region, each of the input-output circuit cells being one of an inner input-output circuit cell and an outer input-output circuit cell;

a first insulating layer covering the semiconductor chip surface;

first signal lines disposed on the first insulating layer and interconnecting the basic cell region and each of the input-output circuit cells;

circuit elements used for forming an input-output interface circuit in conjunction with a selected one of the input-output circuit cells, each of the circuit elements being disposed at a corner of the semiconductor chip surface and the selected input-output circuit cell being an inner one of the input-output circuit cells in the array having at least one associated terminal;

a second insulating layer covering the first insulating layer and the first signal lines;

a plurality of electric power supplying lines formed in parallel to each other on the second insulating layer and extending over the array of input-output circuit cells along the edge of the surface outside the basic cell region; and

a second signal line formed on the second insulating layer, the second signal line being disposed in parallel to and adjacent to one of the power supplying lines and extending over the input-output circuit cells, for interconnecting the circuit element and one of the associated terminals of the predetermined input-output circuit cell, wherein;

each said electric power supplying line has two sides and each of the second signal lines is disposed at one of the two sides of a selected one of the electric power supplying lines;

each of two of the circuit elements is disposed at a respective corner adjacent to a common edge of the semiconductor chip surface; and

the two circuit elements and two respective and associated terminals of the selected input-output circuit cell are interconnected in series by two of the second signal lines.

2. A semiconductor device as set forth in claim 1, wherein one of the two circuit elements is a resistor and the other of the two circuit elements is a capacitor and the input-output interface circuit has a CR time-constant determined based on the resistor and the capacitor.

3. A semiconductor device comprising:

a semiconductor chip having a basic cell region defined at the central area of a surface thereof;

an array of input-output circuit cells arranged along an edge of the surface outside the basic cell region, each of the input-output circuit cells being one of an inner input-output circuit cell and an outer input-output circuit cell;

a first insulating layer covering the semiconductor chip surface;

first signal lines disposed on the first insulating layer and interconnecting the basic cell region and each of the input-output circuit cells;

circuit elements used for forming an input-output interface circuit in conjunction with a selected one of the input-output circuit cells, each of the circuit elements being disposed at a corner of the semiconductor chip surface and the selected input-output circuit cell being an inner one of the input-output circuit cells in the array having at least one associated terminal;

a second insulating layer covering the first insulating layer and the first signal lines;

a plurality of electric power supplying lines formed in parallel to each other on the second insulating layer and extending over the array of input-output circuit cells along the edge of the surface outside the basic cell region; and

a second signal line formed on the second insulating layer, the second signal line being disposed in parallel to and adjacent to one of the power supplying lines and extending over the input-output circuit cells, for interconnecting the circuit element and one of the associated terminals of the predetermined input-output circuit cell, wherein;

each circuit element comprises an insulating-gate field-effect transistor;

the input-output circuit cells comprise formed transistors; and

the insulating-gate field-effect transistor has a larger channel length than a channel length of the formed transistors of the input-output circuit cells.

4. A semiconductor device as set forth in claim 3, wherein the insulating-gate field-effect transistor constitutes a resistor for an input-output interface circuit which comprises the selected input-output circuit cell.

5. A semiconductor device as set forth in claim 4, wherein the input-output interface circuit comprising the selected input-output circuit cell is an oscillation circuit and the resistor is a feedback resistor of the oscillation circuit.

6. A semiconductor device comprising:

a semiconductor chip having a basic cell region defined at the central area of a surface thereof;

an array of input-output circuit cells arranged along an edge of the surface outside the basic cell region, each of the input-output circuit cells being one of an inner input-output circuit cell and an outer input-output circuit cell;

a first insulating layer covering the semiconductor chip surface;

first signal lines disposed on the first insulating layer and interconnecting the basic cell region and each of the input-output circuit cells;

circuit elements used for forming an input-output interface circuit in conjunction with a selected one of the input-output circuit cells, each of the circuit elements being disposed at a corner of the semiconductor chip surface and the selected input-output circuit cell being an inner one of the input-output circuit cells in the array having at least one associated terminal;

a second insulating layer covering the first insulating layer and the first signal lines;

a plurality of electric power supplying lines formed in parallel to each other on the second insulating layer and extending over the array of input-output circuit cells along the edge of the surface outside the basic cell region; and

a second signal line formed on the second insulating layer, the second signal line being disposed in parallel to and adjacent to one of the power supplying lines and extending over the input-output circuit cells, for interconnecting the circuit element and one of the associated terminals of the predetermined input-output circuit cell, two of the circuit elements, wherein

each of two of the circuit elements is disposed at a respective corner adjacent to a common edge of the semiconductor chip surface;

the two circuit elements and one of the associated terminals of the selected input-output circuit cell are interconnected by the second signal line;

one of the two circuit elements is a resistor and the other one of the two circuit elements is a capacitor; and

the input-output interface circuit has a CR time-constant determined based on the resistor and the capacitor.

7. A semiconductor device comprising:

a semiconductor chip having a basic cell region defined at the central area of a surface thereof;

an array of input-output circuit cells arranged along an edge of the surface outside the basic cell region, each of the input-output circuit cells being one of an inner input-output circuit cell and an outer input-output circuit cell;

a first insulating layer covering the semiconductor chip surface;

first signal lines disposed on the first insulating layer and interconnecting the basic cell region and each of the input-output circuit cells;

circuit elements used for forming an input-output interface circuit in conjunction with a selected one of the input-output circuit cells, each of the circuit elements being disposed at a corner of the semiconductor chip surface and the selected input-output circuit cell being an inner one of the input-output circuit cells in the array having at least one associated terminal;

a second insulating layer covering the first insulating layer and the first signal lines;

a plurality of electric power supplying lines formed in parallel to each other on the second insulating layer and extending over the array of input-output circuit cells along the edge of the surface outside the basic cell region;

a second signal line formed on the second insulating layer, the second signal line being disposed in parallel to and adjacent to one of the power supplying lines and extending over the input-output circuit cells, for interconnecting the circuit element and one of the associated terminals of the predetermined input-output circuit cell, wherein the circuit elements comprise a resistor and a capacitor connected in series and the input-output interface circuit has a CR time-constant determined by the resistor and the capacitor.