Bare die carrier

• US 5,402,077 A
• Filed: 11/20/1992
• Issued: 03/28/1995
• Est. Priority Date: 11/20/1992
• Status: Expired due to Term

• Current Assignee: SV Probe Pte Ltd. (Nidec Corporation)
• Original Assignee: Micromodule Systems, Inc.
• Inventors: Ho, Chung W., Agahdel, Fariborz, Husain, Syed, Moti, Robert, Griswold, Brad, Robinette, William C. Jr.
• Primary Examiner(s): Snow, Walter E.
• Assistant Examiner(s): BOWSER, BARRY
• Application Number:
  US07/979,719
• Time in Patent Office: 858 Days
• Field of Search: 324/158 F, 324/158 P, 324/158 R
• US Class Current: 324/756.02
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01067 Holmium [Ho]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

An integrated circuit carrier comprising: a substrate defining an opening and an outer perimeter; a multiplicity of I/O pads disposed about the perimeter; an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed in a polymer dielectric; wherein the interconnect circuit overlays a top surface of the substrate and extends across the opening so as to span the opening; a multiplicity of die contact pads connected to the conductors are disposed about the flexible polymer dielectric with particles deposited on the die contact pads; a polymer dielectric fence upstanding from the membrane and sized to receive an integrated circuit; a top cap that rests upon the integrated circuit when the integrated circuit is received within the fence; a bottom cap that rests against a bottom surface of the substrate; and a fastener for securing the top cap to the bottom cap with the integrated circuit disposed therebetween.

Claims

1. A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuits, comprising:

a substrate which includes an outer perimeter region and an interior region;

a multiplicity of I/O pads disposed in the outer perimeter region of said substrate;

an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a compliant polymer dielectric deposited on a top surface of said substrate;

a fence that is formed integrally with the polymer dielectric and that is sized to receive the die and that upstands from a portion of the polymer dielectric that overlays the interior region;

a multiplicity of die contact pads disposed on a portion of the interconnect circuit within said fence;

wherein said multiplicity of electrical conductors form a multiplicity of electrical paths between said I/O pads and said die contact pads;

a top cap;

a bottom cap; and

means for securing said substrate and the die between said top cap and said bottom cap and for providing a force normal to the substrate;

whereby the normal force compresses the compliant polymer dielectric so as to planarize said die contact pads with respect to each other to improve their contact with the die.

25. The carrier of claims 1, 2, 9, or 24 wherein said fence is formed from a polymer dielectric.

26. The carrier of claim 25 wherein said polymer dielectric forming said fence is photoimagable.

2. A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuits, comprising:

a substrate which includes an inner perimeter which defines an opening and which includes an outer perimeter region;

a multiplicity of I/O pads disposed in the outer perimeter region of said substrate;

an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a polymer dielectric deposited on a top surface of the substrate and extending across the opening;

a fence that is formed integrally with the polymer dielectric and that is sized to receive the die and that upstands from a portion of the polymer dielectric that spans the opening;

a multiplicity of die contact pads disposed on the interconnect circuit within said fence;

wherein said multiplicity of electrical conductors form a multiplicity of electrical paths between said I/O pads and said die contact pads;

a support member which abuts against a bottom surface of said interconnect circuit;

a top cap;

a bottom cap; and

means for securing said substrate and the die between said top cap and said bottom cap with said substrate and the die disposed therebetween.

3. The carrier of claim 2 wherein:

the defined opening is a center opening; and

said interconnect circuit extends across the opening so as to form a flexible membrane that spans the opening.

4. The carrier of claim 2 further including:

a resilient layer;

wherein a bottom surface of said substrate and a bottom surface of said support member rest upon said resilient layer;

wherein the defined opening is a rectangular gap that circumscribes said support member; and

wherein said interconnect circuit spans the gap.

5. The carrier of claim 2 further including:

a multiplicity of hard particles that protrude from the die contact pads in electrical contact with individual conductors.

6. The carrier of claim 2 further including:

force means for applying a prescribed amount of force to an interface of the die and the interconnect circuit.

7. The carrier of claim 2 further including:

a multiplicity of hard particles that protrude from the die contact pads in electrical contact with individual conductors; and

force means for applying a sufficient amount of force to an interface of the die and said interconnect circuit such that individual particles penetrate any nonconductive material formed on the pads of the die.

8. The carrier of claim 2 wherein said support member is formed from a semiconductor material.

20. The carrier of claim 6 wherein:

said force means includes a spring disposed between said support member and said bottom cap.

9. A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuits, comprising:

a substrate defining an opening and an outer perimeter;

a multiplicity of I/O pads disposed about the outer perimeter of said substrate;

an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a polymer dielectric which overlays a top surface of the substrate and which extends across the opening so as to form a flexible membrane that spans the opening;

a multiplicity of die contact pads disposed on the interconnect circuit;

wherein said multiplicity of electrical conductors form a multiplicity of electrical paths between said I/O pads and the die contact pads;

a fence that is formed integrally with the polymer dielectric and that upstands from the polymer dielectric and that is sized to receive the die;

a support member which abuts against a bottom surface of said interconnect circuit;

a top cap;

a bottom cap;

means for securing said substrate and the die and said support member between said top cap and said bottom cap; and

force means for applying a force normal to said support member;

whereby the normal force planarizes said die contact pads with respect to each other to improve their contact with the die.

10. The carrier of claim 9 wherein said support member includes a semiconductor support that abuts against the interconnect circuit.

11. The carrier of claim 9 wherein:

said support member includes a semiconductor support that abuts against the interconnect circuit; and

said force means includes a spring.

12. The carrier of claim 9 wherein the interconnect circuit includes a composite of electrical conductors formed on a polymer dielectric.

13. The carrier of claim 9 wherein said electrically conductive particles are positioned on said die contact pads within said fence so as to make electrical contact with pads of the die when the die is received within said fence.

14. The carrier of claim 9 and further including a spacer that abuts said interconnect circuit and said top cap when the top cap is secured to the bottom with said substrate and with the die secured therebetween.

15. The carrier of claim 9 wherein said top cap is formed from metal.

16. The carrier of claim 9 wherein said top cap and said bottom cap are formed from metal.

17. The carrier of claim 9 further including:

a multiplicity of hard particles that protrude from said die contact pads in electrical contact with individual conductors;

wherein said fence is contoured so as to align the die received within said fence such that respective pads of the die directly overlay respective die contact pads; and

wherein said force means applies sufficient force such that individual particles penetrate any nonconductive material formed on the pads of the die.

18. The carrier of claim 17 wherein the multiplicity of particles are electrically conductive.

19. The carrier of claim 9 wherein a layer of polymer dielectric is formed on a top surface of the semiconductor support.

21. A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuits, comprising:

a substrate defining an opening and an outer perimeter;

a multiplicity of I/O pads disposed about the outer perimeter of said substrate;

an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a polymer dielectric;

wherein said interconnect circuit overlays a top surface of the substrate and extends across the opening;

a multiplicity of die contact pads disposed on the interconnect circuit which form a multiplicity of electrical paths between said I/O pads and the die contact pads in the flexible membrane;

a multiplicity of electrically conductive particles embedded on the die contact pads in contact with individual conductors;

a polymer dielectric fence upstanding from the polymer dielectric and contoured so as to align the die such that respective pads of the die directly overlay respective electrically conductive particles that contact the individual conductors;

a top cap;

a bottom cap;

a support member that abuts against a bottom surface of said interconnect circuit;

force means for applying a sufficient amount of force to an interface of the die and said interconnect circuit such that individual particles penetrate any nonconductive material formed on the pads of the die;

means for securing said substrate and the die between said top cap and said bottom cap.

22. The carrier of claim 21 wherein:

the defined opening is a center opening; and

said interconnect circuit extends across the opening so as to form a flexible membrane that spans the opening.

23. The carrier of claim 21 further including:

a resilient layer;

wherein a bottom surface of said substrate and a bottom surface of said support member rest upon said resilient layer;

wherein the defined opening is a gap that circumscribes said support member; and

wherein said interconnect circuit spans the gap.

24. A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuit, comprising:

a substrate which includes an outer perimeter region and a compliant interior region which is thinner than the outer perimeter region;

a multiplicity of I/O pads disposed in the outer perimeter region of said substrate;

an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a polymer dielectric deposited on a top surface of said substrate;

a fence that is sized to receive the die and that upstands from a portion of the polymer dielectric that overlays the interior region;

a multiplicity of die contact pads disposed on a portion of the interconnect circuit within said fence;

wherein said multiplicity of electrical conductors form a multiplicity of electrical paths between said I/O pads and said die contact pads;

a top cap;

a bottom cap;

means for securing said substrate and the die between said top cap and said bottom cap; and

means for applying a force normal to said substrate;

whereby the normal force pushes said substrate interior toward said semiconductor circuit so as to planarize said die contact pads with respect to each other to improve their connection with the semiconductor circuit.