Precharge device for an integrated circuit internal bus
First Claim
Patent Images
1. An integrated circuit, comprising:
- a plurality of memory sub arrays on a single integrated circuit device;
a local true and complement bit line for each memory sub array;
a local sense amplifier for each sub array, connected to the local true and complement signal lines for each sub array;
a driver circuit for each sub array, connected to an output of the sub array local sense amplifier, and having true and complementary outputs;
a data bus having a true signal line and a complementary signal line, wherein each have a first and second end, wherein the true signal line is connected to the true outputs of each of the driver circuits, and wherein the complementary signal line is connected to the complementary outputs of each of the driver circuits;
means for generating a control signal;
a first precharge device which electrically connects a first location of the true signal line and a first location of the complementary signal line to a preselected voltage supply such that the first precharge device is conductive in response to the control signal; and
a second precharge device, spaced from the first precharge device by a distance approximately equal to a length of the true signal line, which electrically connects a second location of the true signal line and a second location of the complementary signal line to the preselected voltage supply such that the second precharge device is conductive in response to the control signal.
2 Assignments
0 Petitions
Accused Products
Abstract
A method and apparatus for an improved precharge device for an internal bus of an integrated circuit. Multiple precharge devices connect to signal lines throughout an internal bus. The multiple precharge devices are distributed along the internal as opposed to a single precharge device at one end utilized prior thereto. The present invention reduces the time necessary to precharge signal lines due to the decreased effective RC time delay affecting each precharge device.
18 Citations
16 Claims
-
1. An integrated circuit, comprising:
-
a plurality of memory sub arrays on a single integrated circuit device; a local true and complement bit line for each memory sub array; a local sense amplifier for each sub array, connected to the local true and complement signal lines for each sub array; a driver circuit for each sub array, connected to an output of the sub array local sense amplifier, and having true and complementary outputs; a data bus having a true signal line and a complementary signal line, wherein each have a first and second end, wherein the true signal line is connected to the true outputs of each of the driver circuits, and wherein the complementary signal line is connected to the complementary outputs of each of the driver circuits; means for generating a control signal; a first precharge device which electrically connects a first location of the true signal line and a first location of the complementary signal line to a preselected voltage supply such that the first precharge device is conductive in response to the control signal; and a second precharge device, spaced from the first precharge device by a distance approximately equal to a length of the true signal line, which electrically connects a second location of the true signal line and a second location of the complementary signal line to the preselected voltage supply such that the second precharge device is conductive in response to the control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. An integrated circuit, comprising:
-
a plurality of memory sub arrays on a single integrated circuit device; a plurality of local true and complement bit lines for each memory sub array; a plurality of local sense amplifiers for each sub array, connected to the local true and complement signal lines for each sub array; a plurality of driver circuits for each sub array, connected to outputs of the sub array local sense amplifiers, and having true and complementary outputs; a plurality of true signal lines and a plurality of complementary signal lines, wherein each of the complementary signal lines is associated with one of the true signal lines to form a pair, wherein each true signal line is connected to the true outputs of one of the driver circuits for each sub array, and wherein each complementary signal line is connected to the complementary outputs of one of the driver circuits for each sub array; a plurality of sense amplifiers, wherein each of the sense amplifiers is associated with one of the pairs of the true and complementary signal lines, and wherein each of the sense amplifiers has a first output for driving the true signal line in the associated pair to a first value, and a second output for driving the complementary signal line in the associated pair to a complementary signal value; and a plurality of precharge devices associated with each of the pairs of the true and complementary signal lines and distributed along the length of the signal lines, wherein each of the precharge devices charges the true and complementary signal lines to a preselected value upon receipt of a control signal. - View Dependent Claims (11, 12, 13, 14, 15, 16)
-
Specification