Apparatus for quantizing pixel information to an output video display space

• US 5,402,506 A
• Filed: 06/23/1994
• Issued: 03/28/1995
• Est. Priority Date: 10/15/1991
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: Pixel Semiconductor, Inc.
• Inventors: Schafer, John C.
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): Johns, Andrew W.
• Application Number:
  US08/265,496
• Time in Patent Office: 278 Days
• Field of Search: 382/50, 358/455, 358/456, 358/458, 358/461, 358/463
• US Class Current: 382/270
• CPC Class Codes: G06T 9/005 Statistical coding, e.g. Huffman, run length coding
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/14 Display of multiple viewports

Abstract

A quantization processor (64) is provided that is operable to provide an error diffusion for adjacent output pixels in an output display space. Three quantization processors (300), (302) and (304) are provided for the three colors of the video RGB format. A full adder (312) is provided for receiving both an error signal and an input pixel value. The composite output is input to an input/output error register 328 that is operable to store bits of the output of the adder, determined to be output bits, and also to store the remainder of the bits that are determined to be error or truncated bits. The error or truncated bits are fed back to the input of the full adder. A rounding decoder (306) is operable to receiving a masking word, such that the outputs from the register (326) are either selected as bits to be truncated, provide an error to be added to the next sequential pixel value, or they are selected as outputs. The register (326) is operable to store the error bits for the next sequential cycle.

Claims

1. Quantization circuitry comprising:

a bus having plurality of lines each for carrying a masking bit;

an adder having a first plurality of inputs for receiving respective ones of plurality of parallel input pixel data bits, a second plurality of inputs, a saturation signal output and a plurality of data outputs;

a first NOR gate having a first input coupled to a most significant bit one of said plurality of data outputs of said adder and a second input coupled to said saturation signal output of said adder;

a first plurality of AND gates each having a first input coupled to said saturation output of said adder and a second input coupled to a respective one of said plurality of lines of said bus;

a second plurality of NOR gates each having a first input coupled to an output of a corresponding one of said AND gates and a second input coupled to a corresponding lesser significant bit one of said plurality of data outputs of said adder;

a register having a most significant bit input, a plurality of lesser significant bit inputs, a most significant bit output and a plurality of lesser significant bit outputs, said most significant bit input coupled to an output of said first NOR gate and said lesser significant bit inputs each coupled to an output of a respective one of said second plurality of NOR gates;

a third plurality of NOR gates each having a first input coupled to a respective one of said plurality of lines of said bus, a second input coupled to a respective one of said plurality of lesser significant bit outputs of said register, and a output coupled to a respective one of said plurality of second inputs of said adder, said adder operable to add bits received at said plurality of second inputs of said adder with bits received at said plurality of first inputs of a said adder;

a most significant bit output gate coupled to said most significant bit output of said register; and

a plurality of lesser significant bit output AND gates each having a first input coupled to a respective line of said bus and a second inverting input coupled to a respective one of said plurality of lesser significant bit outputs of said register.

2. The circuitry of claim 1 and further comprising:

A NOR gate having a first input coupled to a next most significant bit one of said plurality of data outputs of said adder, a second input coupled to said saturation signal output of said adder, and an output coupled to a next most significant bit input of said register; and

a next most significant bit output gate coupled to a next most significant bit output of said register.

3. The circuitry of claim 2 wherein said next most significant bit output gate comprises an AND gate having a first input coupled to a voltage level and a second inverting input coupled to said next most significant bit output of said register.

4. The circuitry of claim 1 wherein said most significant bit output gate comprises an AND gate having a first input coupled to a voltage level and a second inverting input coupled to said most significant bit output of said register.

5. The circuitry of claim 1 wherein said plurality of bits form a word defining a level of a color of a corresponding pixel to be displayed.

6. The circuitry of claim 5 wherein said color is selected from the group consisting of red, blue and green.

7. Quantization circuitry comprising:

a bus including a line for carrying an masking bit;

an adder having a first input for receiving a stream of bits of pixel data each clocked by a clock signal;

a first NOR gate having a first input coupled to a most significant bit data output of said adder and a second input coupled to a saturation signal output of said adder;

a first AND gate having a first input coupled to said saturation output of said adder and a second input coupled to a said line of said bus;

a second NOR gate having a first input coupled to an output of said first AND gate and a second input coupled to a lesser significant bit data output of said adder;

a register having a most significant bit input coupled to an output of said first NOR gate and a lesser significant bit input coupled to an output of said second gate;

a third NOR gate having a first input coupled to said line of said bus, a second input coupled to a lesser significant bit output of said register, and a output coupled to a second input of said adder;

a most significant bit output gate coupled to a most significant bit output of said register;

a lesser significant bit output AND gate having a first input coupled to said line of said bus and a second inverting input coupled to said lesser significant bit output of said register; and

wherein said register is operable to store a bit received at said lesser significant bit input for a period of said clock signal before presenting said bit at said lesser significant bit output and said adder is operable to add a bit received at said second input of said adder with a bit received at a first input of said adder.

8. The circuitry of claim 7 wherein each bit of said stream of bits comprises a portion of a word of pixel data.

9. The circuitry of claim 8 wherein said word defines a color level of a pixel to be displayed.

10. The circuitry of claim 7 wherein said stream of bits of pixel data is received substantially in real time.