Structure and fabrication of power MOSFETs, including termination structures

• US 5,404,040 A
• Filed: 07/22/1993
• Issued: 04/04/1995
• Est. Priority Date: 12/21/1990
• Status: Expired due to Fees

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Linde, Jan V. D., Hshieh, Fwu-Iuan, Chang, Mike, Owyang, King, Pitzer, Dorman C., Chen, Jun W.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/096,135
• Time in Patent Office: 621 Days
• Field of Search: 257/341, 257/377, 257/382, 257/401, 257/412, 257/620, 257/754, 257/773, 437/40, 437/49, 437/186, 437/189, 437/228, 437/233, 437/913
• US Class Current: 257/341
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/3221 of silicon bodies, e.g. for gettering
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002) of substantially uniform thickness lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.

A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. The MOSFET is typically created by a five-mask process. A defreckle etch is performed subsequent to metal deposition and patterning to define the two peripheral polycrystalline segments.

Claims

1. A power MOSFET comprising:

a monocrystalline semiconductor body having a main active area and a peripheral termination area;

a plurality of source regions situated in the active area;

a first insulating layer overlying the active and termination areas;

a main polycrystalline semiconductor portion situated over the first insulating layer largely above the active area;

a peripheral polycrystalline semiconductor segment situated over the first insulating layer above the termination area and laterally separated from the main polycrystalline portion;

a second insulating layer overlying the main polycrystalline portion and the peripheral polycrystalline segment;

a gate electrode contacting the main polycrystalline portion through at least one opening in the second insulating layer;

a source electrode contacting the source regions through a plurality of openings in the insulating layers; and

a metallic portion contacting the peripheral polycrystalline segment through at least one opening in the second insulating layer, the metallic portion being laterally separated from the source and gate electrodes, the peripheral polycrystalline segment extending over a scribe-line section of the termination area so as to be scribed during a scribing operation.

2. A power MOSFET as in claim 1 wherein the second insulating layer also extends over the scribe-line section so as to be scribed during the scribing operation.

3. A power MOSFET as in claim 1 wherein the peripheral polycrystalline segment substantially laterally surrounds the main polycrystalline portion.

4. A power MOSFET as in claim 1 wherein the metallic portion substantially laterally surrounds the source and gate electrodes.

5. A power MOSFET as in claim 1 wherein the metallic portion is vertically spaced apart from the termination area.

6. A method which comprises the following steps for creating a power MOSFET:

forming a non-monocrystalline semiconductor layer over a first insulating layer along a monocrystalline semiconductor body having a main active area and a peripheral termination area, the semiconductor body being of a first conductivity type;

patterning the non-monocrystalline layer to form therethrough (a) a plurality of openings situated over the active area and (b) an annular opening situated over the termination area and substantially laterally surrounding the openings over the active area so as to divide the non-monocrystalline layer into (b1) a main non-monocrystalline portion largely overlying the active area and (b2) a laterally separate peripheral non-monocrystalline portion overlying the termination area;

introducing a dopant of a second conductivity type opposite to the first conductivity type through the openings into the semiconductor body to form (a) a like plurality of body regions of the second conductivity type in the active area and (b) a field plate region of the second conductivity type in the termination area;

selectively introducing a dopant of the first conductivity type through the plurality of openings over the active area into the semiconductor body, but substantially not through the annular opening over the termination area, to form source regions of the first conductivity type in the body regions;

forming a second insulating layer over the non-monocrystalline portions and in the openings;

selectively removing parts of at least the second of the insulating layers to form therethrough (a) a like plurality of further openings down to the source regions, (b) a further opening down to the field plate region, (c) at least one further opening down to the main non-monocrystalline portion, and (d) at least one further opening down to the peripheral non-monocrystalline portion;

depositing a metallic layer over the second insulating layer and into the further openings;

patterning the metallic layer to form (a) a gate electrode that contacts the main non-monocrystalline portion and (b) a source electrode that contacts the source regions, the field plate region, and the peripheral non-monocrystalline portion; and

forming a drain electrode that contacts the semiconductor body.

7. A method as in claim 6 wherein the first insulating layer is of substantially uniform thickness.

8. A method as in claim 7 wherein the thickness of the first insulating layer is 100-1000 angstroms.

9. A method as in claim 6 further including the step of introducing a dopant of the second conductivity type through the further openings to form (a) a like plurality of more heavily doped body contact zones respectively continuous with the body regions and (b) a more heavily doped field plate contact zone continuous with the field plate region.

10. A method as in claim 9 wherein the source electrode contacts the contact zones.

11. A method as in claim 6 further including the step of etching the peripheral non-monocrystalline portion through at least a substantially annular part of a further opening formed through the second insulating layer in order to divide the peripheral non-monocrystalline portion into (a) a first non-monocrystalline segment that contacts the source electrode and substantially laterally surrounds the active area and (b) a laterally separated second non-monocrystalline segment that substantially laterally surrounds the first non-monocrystalline segment.

12. A method as in claim 11 wherein substantially the entire portion of the metallic layer over the second non-monocrystalline segment is removed during the metallic-layer patterning step.

13. A method as in claim 11 wherein an additional portion of the metallic layer is left over at least part of the second non-monocrystalline segment during the metallic-layer patterning step.

14. A method as in claim 13 wherein the additional portion of the metallic layer is formed so as to be vertically spaced apart from the termination area.

15. A method which comprises the following steps for creating a termination structure for a power MOSFET:

forming a first insulating layer along an upper surface of a monocrystalline semiconductor body of a first conductivity type having a main active area and a peripheral termination area;

depositing a non-monocrystalline semiconductor layer over the first insulating layer;

forming an opening at least partway through the non-monocrystalline layer over the termination area;

introducing a dopant of a second conductivity type opposite to the first conductivity type through the opening into the semiconductor body to form a field plate region of the second conductivity type in the termination area;

forming a second insulating layer along the non-monocrystalline layer and over the opening;

selectively removing portions of at least the second of the insulating layers to expose (a) at least one part of the field plate region and (b) at least one part of the non-monocrystalline layer over the termination area;

creating a patterned layer of conductive material over the insulating layers such that a unitary portion of the conductive material contacts both the field plate region and the non-monocrystalline layer over the termination area, an exposed portion of the non-monocrystalline layer over the termination area substantially laterally surrounding both the active area and the unitary portion of the conductive material; and

subsequently etching the non-monocrystalline layer at the exposed portion to divide material of the non-monocrystalline layer over the termination area into (a) a first non-monocrystalline segment that contacts the unitary portion of the conductive material and (b) a laterally separated second non-monocrystalline segment that substantially laterally surrounds the first non-monocrystalline segment.

16. A method as in claim 15 wherein the non-monocrystalline and patterned layers respectively consist principally of polysilicon and metal.

17. A method as in claim 15 wherein substantially none of the conductive material overlies the second non-monocrystalline segment at the end of the creating step.

18. A method as in claim 15 wherein an additional portion of the conductive material is left over at least part of the second non-monocrystalline segment at the end of the creating step.

19. A method as in claim 15 wherein the exposed portion of the non-monocrystalline layer is laterally separated from where the unitary portion of the conductive material contacts the non-monocrystalline layer.

20. A method which comprises the following steps for creating a termination structure for a power MOSFET:

forming a first insulating layer along an upper surface of a monocrystalline semiconductor body having a main active area and a peripheral termination area;

depositing a non-monocrystalline semiconductor layer over the first insulating layer;

forming a second insulating layer along the non-monocrystalline layer;

selectively removing material of the second insulating layer to expose at least one part of the non-monocrystalline layer over the termination area;

depositing a conductive layer over the second insulating layer and over exposed material of the non-monocrystalline layer;

patterning the conductive layer to form source and gate electrodes and a laterally separate special conductive portion which (a) substantially laterally surrounds the source and gate electrodes and (b) contacts the non-monocrystalline layer over the termination area, an exposed portion of the non-monocrystalline layer over the termination area substantially laterally surrounding the active area; and

etching the non-monocrystalline layer at the exposed portion to divide material of the non-monocrystalline layer over the termination area into a first non-monocrystalline segment and a laterally separate second non-monocrystalline segment that substantially laterally surrounds the first non-monocrystalline segment.

21. A method as in claim 20 wherein the non-monocrystalline and conductive layers respectively consist principally of polysilicon and metal.

22. A method as in claim 20 further including the step of introducing dopants into the active area for creating active MOSFET cells.

23. A method as in claim 20 wherein a portion of the source electrode is formed during the patterning step so as to contact the non-monocrystalline layer over the termination area.

24. A method as in claim 23 wherein the exposed portion of the non-monocrystalline layer is laterally separated from where the source electrode contacts the non-monocrystalline layer.

25. A method as in claim 20 wherein the special portion of the conductive layer is formed so as to be vertically spaced apart from the termination area.

26. A method which comprises the following steps for creating a power MOSFET:

forming a non-monocrystalline semiconductor layer over a first insulating layer along a semiconductor body of a first conductivity type having a main active area and a peripheral termination area;

patterning the non-monocrystalline layer to form (a) a plurality of openings situated over the active area and (b) an opening situated over the termination area and substantially laterally surrounding the openings over the active area so as to divide the non-monocrystalline layer into (b1) a main non-monocrystalline portion largely overlying the active area and (b2) a laterally separate peripheral non-monocrystalline portion overlying the termination area;

introducing a dopant of a second conductivity type opposite to the first conductivity type through the openings into the semiconductor body to form (a) a like plurality of body regions of the second conductivity type in the active area and (b) a field plate region of the second conductivity type in the termination area;

selectively introducing a dopant of the first conductivity type through the plurality of openings over the active area into the semiconductor body, but substantially not through the opening over the termination area, to form source regions of the first conductivity type in the body regions;

forming a second insulating layer over the non-monocrystalline portions and in the openings;

selectively removing portions of at least the second of the insulating layers to expose at least one part of each of the source regions, the field plate region, and the two non-monocrystalline portions; and

creating (a) a gate electrode that contacts the main non-monocrystalline portion, (b) a source electrode that contacts the source regions, the field plate region, and the peripheral non-monocrystalline portion, and (c) a drain electrode that contacts the semiconductor body.

27. A method as in claim 26 further including the step of etching the peripheral non-monocrystalline portion through an annular opening formed through the second insulating layer during or after the selectively removing step in order to divide the peripheral non-monocrystalline portion into (a) a first non-monocrystalline segment that contacts the source electrode and substantially laterally surrounds the active area and (b) a laterally separated second non-monocrystalline segment that substantially laterally surrounds the first non-monocrystalline segment.

28. A method as in claim 26 wherein the thickness of the first insulating layer is 100-1000 angstroms.

29. A method as in claim 26 further including the step of introducing a dopant of the second conductivity type through openings created during or after the selectively removing step to form (a) a like plurality of more heavily doped body contact zones respectively continuous with the body regions and (b) a more heavily doped field plate contact zone continuous with the field plate region.

30. A method as in claim 29 wherein the source electrode contacts the contact zones.

31. A method as in claim 26 wherein the creating step comprises:

depositing a conductive layer over the insulating layer so as to contact the source regions, the field plate region, and both non-monocrystalline portions;

patterning the conductive layer to form the gate and source electrodes; and

separately forming the drain electrode to contact the semiconductor body at a location spaced apart from the source regions, the field plate region, and the two non-monocrystalline portions.