Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit
First Claim
1. An ESD/EOS protection circuit for protecting an integrated circuit comprising:
- a. a MOS transistor having a drain region, a source region and a gate;
b. at least one source contact located above said source region at a first distance from said gate, wherein said at least one source contact comprises a plurality of source contacts arranged into a plurality of rows and columns;
c. at least one drain contact located above said drain region at a second distance from said gate, wherein said first distance is smaller than said second distance.
2 Assignments
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Accused Products
Abstract
An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).
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Citations
13 Claims
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1. An ESD/EOS protection circuit for protecting an integrated circuit comprising:
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a. a MOS transistor having a drain region, a source region and a gate; b. at least one source contact located above said source region at a first distance from said gate, wherein said at least one source contact comprises a plurality of source contacts arranged into a plurality of rows and columns; c. at least one drain contact located above said drain region at a second distance from said gate, wherein said first distance is smaller than said second distance. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An ESD/EOS protection circuit for protecting an integrated circuit comprising:
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a. a MOS transistor arranged in a multi-finger configuration having a plurality of drain regions, a plurality of source regions and a plurality of gates, wherein each of said gates is located between one of said source regions and one of said drain regions; b. a plurality of source contacts located above each of said source regions at a first distance from at least one of said plurality of gates; c. a plurality of drain contacts located above each of said drain regions at a second distance from at least one of said plurality of gates, wherein said first distance is smaller than said second distance; d. a first metal layer extending over and substantially covering each of said drain regions and in contact with each of said drain regions via said plurality of drain contacts; e. a second metal layer extending over and substantially covering each of said source regions and in contact with each of said source regions via said plurality of source contacts; f. a third metal layer extending over and substantially covering said MOS transistor; and g. a plurality of metal-to-metal contacts for connecting said third metal layer with said second metal layer over each of said source regions. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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Specification