Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit

• US 5,404,041 A
• Filed: 03/31/1993
• Issued: 04/04/1995
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Board of Trustees of The University of Illinois, Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Diaz, Carlos H., Kang, Sung-Mo, Duvvury, Charvaka
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/040,957
• Time in Patent Office: 734 Days
• Field of Search: 257/360, 257/401, 257/758, 257/773, 361/56, 361/91
• US Class Current: 257/360
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).

Claims

1. An ESD/EOS protection circuit for protecting an integrated circuit comprising:

a. a MOS transistor having a drain region, a source region and a gate;

b. at least one source contact located above said source region at a first distance from said gate, wherein said at least one source contact comprises a plurality of source contacts arranged into a plurality of rows and columns;

c. at least one drain contact located above said drain region at a second distance from said gate, wherein said first distance is smaller than said second distance.

2. The ESD/EOS protection circuit of claim 1, wherein said source region and said drain region comprise approximately the same amount of area.

3. The ESD/EOS protection circuit of claim 1, wherein said first distance is less than 2 microns.

4. The ESD/EOS protection circuit of claim 1, wherein said first distance is a lithographic minimum distance.

5. The ESD/EOS protection circuit of claim 1, wherein said at least one drain contact comprises a plurality of drain contacts arranged in a row.

6. The ESD/EOS protection circuit of claim 1, further comprising:

a. a first metal layer extending over said drain region and in contact with said drain region via said at least one drain contact;

b. a second metal layer extending over said source region and in contact with said source region via said at least one source contact;

c. a third metal layer extending over said MOS transistor; and

d. a plurality of metal-to-metal contacts for connecting said third metal layer with said second metal layer.

7. An ESD/EOS protection circuit for protecting an integrated circuit comprising:

a. a MOS transistor arranged in a multi-finger configuration having a plurality of drain regions, a plurality of source regions and a plurality of gates, wherein each of said gates is located between one of said source regions and one of said drain regions;

b. a plurality of source contacts located above each of said source regions at a first distance from at least one of said plurality of gates;

c. a plurality of drain contacts located above each of said drain regions at a second distance from at least one of said plurality of gates, wherein said first distance is smaller than said second distance;

d. a first metal layer extending over and substantially covering each of said drain regions and in contact with each of said drain regions via said plurality of drain contacts;

e. a second metal layer extending over and substantially covering each of said source regions and in contact with each of said source regions via said plurality of source contacts;

f. a third metal layer extending over and substantially covering said MOS transistor; and

g. a plurality of metal-to-metal contacts for connecting said third metal layer with said second metal layer over each of said source regions.

8. The ESD/EOS protection circuit of claim 7, wherein said plurality of source regions and said plurality of drain regions comprise approximately the same amount of area.

9. The ESD/EOS protection circuit of claim 7, wherein said first distance is less than 2 microns.

10. The ESD/EOS protection circuit of claim 7, wherein said first distance is a design minimum.

11. The ESD/EOS protection circuit of claim 7, wherein said plurality of drain contacts are arranged in a row above each of said drain regions.

12. The ESD/EOS protection circuit of claim 7, wherein said third metal layer is connected to a ground and said first metal layer is connected to a protected pad.

13. The ESD/EOS protection circuit of claim 7, wherein said plurality of source contacts and said plurality of metal-to-metal contacts are arranged in a plurality of alternating rows over each of said source regions.