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Parallel process interposer (PPI)

  • US 5,404,044 A
  • Filed: 11/17/1993
  • Issued: 04/04/1995
  • Est. Priority Date: 09/29/1992
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit chip interposer having a plurality of interposer layers comprised of:

  • a di-electric layer;

    a first conductive plane on a top surface of said di-electric layer;

    a second conductive plane on a bottom surface of said di-electric layer;

    an adhesive layer coating each said conductive plane;

    a plurality of conductive vias through said di-electric layer;

    a conductive adhesive in each said via; and

    said plurality of interposer layers in a stack, said stack of interposer layers being bonded together by said conductive adhesive in each said via.

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