Parallel process interposer (PPI)

• US 5,404,044 A
• Filed: 11/17/1993
• Issued: 04/04/1995
• Est. Priority Date: 09/29/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Booth, Richard B., Gremban, Bradley S., Gephard, Robert H., Poetzinger, Janet E., Shen, David T.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/154,312
• Time in Patent Office: 503 Days
• Field of Search: 257/777, 257/778, 257/700, 257/691, 257/698, 257/685, 257/686, 257/723, 257/724, 174/258
• US Class Current: 257/698
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0272 Adaptations for fluid transport, e.g. channels, holes
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/09436 Pads or lands on permanent coating which covers the other conductors
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/09845 Stepped hole, via, edge, bump or conductor
• CPC Class Codes: H05K 2201/10378 Interposers
• CPC Class Codes: H05K 3/225 Correcting or repairing of printed circuits H05K1/0292, H05K3/222, H05K3/288, H05K3/4685 take precedence
• CPC Class Codes: H05K 3/321 by conductive adhesives
• CPC Class Codes: H05K 3/368 parallel to each other H05K3/361 takes precedence
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/462 characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49726 Removing material
• CPC Class Codes: Y10T 29/4973 : Replacing of defective part

Abstract

A multilayer, high yield and high density integrated circuit (IC) chips interposer and the method of manufacture therefore. A thin polyimide film is circuitized with copper on both sides. One side may be reserved for power or ground with the opposite side being a signal plane. Adhesive is laminated over both sides covering the circuit patterns. Vias are drilled through at least one adhesive surface, and through the polyimide film. Metal (copper) is blanket sputtered to coat the via walls. Polymer Metal Conductive (PMC) paste is screened to at least partially fill the vias. The Blanket metal is sub-etched using the screened PMC as a mask. Layers are stacked to form the interposer with the PMC bonding the stacked layers together and electrically interconnecting between layers.

Claims

1. An integrated circuit chip interposer having a plurality of interposer layers comprised of:

a di-electric layer;

a first conductive plane on a top surface of said di-electric layer;

a second conductive plane on a bottom surface of said di-electric layer;

an adhesive layer coating each said conductive plane;

a plurality of conductive vias through said di-electric layer;

a conductive adhesive in each said via; and

said plurality of interposer layers in a stack, said stack of interposer layers being bonded together by said conductive adhesive in each said via.

2. The integrated circuit chip interposer of claim 1 further comprising a cap at one end of said stack.

3. The integrated circuit chip interposer of claim 1 wherein said di-electric layer is a polyimide layer.

4. The integrated circuit chip interposer of claim 1 wherein said first and second conductive planes are copper.

5. The integrated circuit chip interposer of claim 1 wherein said first conductive plane is a signal distribution plane and said second conductive plane is a power of ground distribution plane.

6. The interposer of claim 1 wherein said adhesive layer is comprised of a first soluble thermoplastic material and said conductive adhesive is comprised of a second soluble thermoplastic material.

7. An integrated circuit chip package comprised of:

an interposer having a plurality of interposer layers comprised of;

a di-electric layer,

a conductive plane on a top surface of said di-electric layer,

a conductive plane on a bottom surface of said di-electric layer,

each said conductive layer being coated by an adhesive coating,

a plurality of conductive vias through said di-electric layer, and,

a conductive adhesive paste in each said via,

said plurality of layers in a stack, said stacked layers being bonded together by said conductive adhesive paste; and

,

a substrate, said interposer being mounted on said substrate.

8. The integrated circuit chip package of claim 7 further comprising a cap at one end of said interposer stack.

9. The integrated circuit chip package of claim 7 wherein said interposer'"'"'s di-electric layer is a polyimide layer.

10. The integrated circuit chip package of claim 7 wherein said first and said second conductive planes are copper.

11. The integrated circuit chip interposer of claim 7 wherein said first conductive plane is a signal distribution plane and said second conductive plane is a power or ground distribution plane.