Parallel process interposer (PPI)
First Claim
1. An integrated circuit chip interposer having a plurality of interposer layers comprised of:
- a di-electric layer;
a first conductive plane on a top surface of said di-electric layer;
a second conductive plane on a bottom surface of said di-electric layer;
an adhesive layer coating each said conductive plane;
a plurality of conductive vias through said di-electric layer;
a conductive adhesive in each said via; and
said plurality of interposer layers in a stack, said stack of interposer layers being bonded together by said conductive adhesive in each said via.
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Accused Products
Abstract
A multilayer, high yield and high density integrated circuit (IC) chips interposer and the method of manufacture therefore. A thin polyimide film is circuitized with copper on both sides. One side may be reserved for power or ground with the opposite side being a signal plane. Adhesive is laminated over both sides covering the circuit patterns. Vias are drilled through at least one adhesive surface, and through the polyimide film. Metal (copper) is blanket sputtered to coat the via walls. Polymer Metal Conductive (PMC) paste is screened to at least partially fill the vias. The Blanket metal is sub-etched using the screened PMC as a mask. Layers are stacked to form the interposer with the PMC bonding the stacked layers together and electrically interconnecting between layers.
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Citations
11 Claims
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1. An integrated circuit chip interposer having a plurality of interposer layers comprised of:
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a di-electric layer; a first conductive plane on a top surface of said di-electric layer; a second conductive plane on a bottom surface of said di-electric layer; an adhesive layer coating each said conductive plane; a plurality of conductive vias through said di-electric layer; a conductive adhesive in each said via; and said plurality of interposer layers in a stack, said stack of interposer layers being bonded together by said conductive adhesive in each said via. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit chip package comprised of:
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an interposer having a plurality of interposer layers comprised of; a di-electric layer, a conductive plane on a top surface of said di-electric layer, a conductive plane on a bottom surface of said di-electric layer, each said conductive layer being coated by an adhesive coating, a plurality of conductive vias through said di-electric layer, and, a conductive adhesive paste in each said via, said plurality of layers in a stack, said stacked layers being bonded together by said conductive adhesive paste; and
,a substrate, said interposer being mounted on said substrate. - View Dependent Claims (8, 9, 10, 11)
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Specification