Fuse blow circuit

• US 5,404,049 A
• Filed: 11/02/1993
• Issued: 04/04/1995
• Est. Priority Date: 11/02/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Canada, Miles G., Rawlins, John R., Rivadeneira, Carlos G., Nicewicz, Michael
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US08/146,253
• Time in Patent Office: 518 Days
• Field of Search: 307/202.1, 307/465, 365/96, 365/225.7
• US Class Current: 327/525
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A chip can be provide with circuits to electrically read, blow and latch fuses. The circuit allows use of existing I/O pads used for other functions on a chip to drastically reduce the number of I/O required to blow fuses. The circuits also share critical high current carrying lines with no impact on fuse functionality and device reliability. By offering of complex fuse operations such as electrical override, even after they had been blown, essential for product screening and product diagnostics. The circuit provides a fuse blow circuit fed by a fuse sense circuit and fuse latch circuit. Stored addresses in an address buffer addresses the fuses with two sets of inputs: one providing electrical override and/or fuse blow information; and the second one, normal fuse status. Fuse integrity before and after blow is maximized with a dual voltage source drive and low current sensing.

Claims

1. A fuse blow circuit for a VLSI chip comprising:

a VLSI chip substrate having a plurality of fuses coupled to a fuse control circuit;

said VLSI chip having a plurality of I/O terminal pads used for other functions on said chip and coupled between the fuses and the fuse control circuit to enable addressing the fuses so that the fuses can be read, blown or electrically bypassed,

a fuse latch-blow circuit on said chip having a fuse blow circuit, a fuse sense circuit, a fuse latch circuit, and I/O address buffers, and wherein

said fuse control circuit and fuse latch-blow circuit provides means for permanently reading outputs from the I/O address buffers and the fuse sense circuit and for loading either one of those into the fuse latch circuit, whereby

said fuse latch circuit will output the state of an address or a fuse according to the instructions of said fuse control circuit.

2. A fuse blow circuit according to claim 1 wherein

a fuse has a first terminal providing a first fuse voltage I/O connection pad, and a second terminal coupled to said fuse blow circuit and also coupled to said fuse sense circuit,

said fuse blow circuit is coupled to a second fuse voltage I/O connection pad

said fuse sense circuit is coupled to said fuse blow circuit;

and

said fuse latch circuit is coupled to said fuse sense circuit having at least three inputs and having outputs differentially coupled to a first input to said fuse blow circuit, the output of said fuse blow circuit being coupled to an output of said second terminal of said fuse and also coupled to the input of said fuse sense circuit, and wherein a second input of said fuse blow circuit is coupled to said second fuse voltage I/O connection pad, and an output of the fuse sense circuit is coupled to a first input of the fuse latch circuit,

and said address buffer for a fuse stores addresses, said address buffer having an output coupled to a second input of said fuse latch circuit, and

wherein said fuse control circuit is provided for firing a fuse and has three outputs differentially coupled to a third input of said fuse latch circuit, and also has a first and second control signal inputs.

3. A fuse blow circuit according to claim 1 wherein there are a plurality of fuses and fuse latch, fuse blow and fuse sense circuits provided, and wherein said fuse control circuit is shared with other fuses.

4. A fuse blow circuit according to claim 1 wherein there are a plurality of fuses and fuse latch, fuse blow and fuse sense circuits provided, and wherein said fuse control circuit is be shared with other fuses, and said address buffer is provided for each fuse and can perform other functions on the VLSI chip.

5. A fuse blow circuit according to claim 1 wherein said fuse latch is coupled to a fuse sense and address buffer and has inputs from the outputs of said fuse sense and address buffer for passing inputs of said fuse sense during a read fuse operation and inputs of said address buffer during an override fuse and/or fuse blow operation, and has means for permanently latching either of said inputs after it has been initialized according to instructions of the fuse control circuit.

6. A fuse blow circuit according to claim 2 wherein said first and second fuse voltages are switched in opposite directions during a fuse blow operation;

said first fuse voltage must be coupled to VCC during a normal operation and should go to a higher value than VCC during such blow operation, said second fuse voltage floats during a normal operation and is passed to VEE during such blow operation.

7. A fuse blow circuit according to claim 1 wherein said fuse is read using a trickle current.

8. A fuse blow circuit according to claim 1 wherein said fuse is read using a trickle current provided by a current mirror transistor and a bias voltage reference.

9. A fuse blow circuit according to claim 7 wherein there are a plurality of fuses and fuse latch, fuse blow and fuse sense circuit provided, and wherein said fuse control circuit is be shared with other fuses.

10. A fuse blow circuit according to claim 9 wherein there are a plurality of fuses and fuse latch, fuse blow and fuse sense circuits provided, and wherein said fuse control circuit is be shared with other fuses, and an address buffer is provided for each fuse and can perform other functions on the VLSI chip.

11. A fuse blow circuit according to claim 10 wherein said fuse latch is coupled to said fuse sense and address buffer and has inputs from the outputs of said fuse sense and address buffer circuits for passing inputs of said fuse sense during a read fuse operation and inputs of said address buffer during an override fuse and/or fuse blow operation, and has means for permanently latching either of said inputs after it has been initialized according to instructions of the fuse control circuit.

12. A fuse blow circuit according to claim 11 wherein said first and second terminal I/O voltages are switched in opposite directions during a fuse blow operation;

said first terminal voltage must be coupled to VCC during a normal operation and should go to a higher value than VCC during such blow operation, said second terminal I/O voltage floats float during a normal operation and is passed to VEE during such blow operation.

13. A fuse blow circuit according to claim 12 wherein said fuse is read using a trickle current provided by a current mirror transistor and a bias voltage reference.

14. A fuse blow circuit according to claim 13 wherein said I/O voltages can be shared with a bank of fuses and fuse blow circuits.