Anti-noise and auto-stand-by memory architecture
First Claim
1. A method for extracting data from a memory, the memory having a delay of propagation of the signals therethrough, comprising:
- detecting every transition of memory address signals and generating a first pulse for any detected transition;
enabling by means of a reset signal a dummy circuit chain having a dummy sense amplifier therein, which reproduces a signal propagation path through the memory and a sense amplifier thereof;
propagating said generated first pulse through said enabled dummy circuit chain; and
generating a second pulse capable of enabling an extracted data output storing circuit and disabling said enabled dummy chain, at the end of the propagation of one address signal transition detecting pulse through said enabled dummy chain.
1 Assignment
0 Petitions
Accused Products
Abstract
Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by simplifying the sensing process.
24 Citations
17 Claims
-
1. A method for extracting data from a memory, the memory having a delay of propagation of the signals therethrough, comprising:
-
detecting every transition of memory address signals and generating a first pulse for any detected transition; enabling by means of a reset signal a dummy circuit chain having a dummy sense amplifier therein, which reproduces a signal propagation path through the memory and a sense amplifier thereof; propagating said generated first pulse through said enabled dummy circuit chain; and generating a second pulse capable of enabling an extracted data output storing circuit and disabling said enabled dummy chain, at the end of the propagation of one address signal transition detecting pulse through said enabled dummy chain.
-
-
2. A method for extracting data from a memory, the memory including power dissipating structures and having a delay of propagation for the signals therethrough, comprising:
-
detecting every transition of memory address signals and generating a first pulse for any detected transition; enabling by means of a reset signal a dummy circuit chain which reproduces a signal propagation path through the memory and a sense amplifier thereof and power dissipating structures of said memory; propagating said generated first pulse through said enabled dummy circuit chain; and generating a second pulse capable of enabling an extracted data output storing circuit and disabling said enabled dummy chain and said power dissipating structures of said memory, at the end of the propagation of one address signal transition detecting pulse through said enabled dummy chain.
-
-
3. A memory device comprising, functionally organized in cascade, at least an input circuitry, a control circuitry, a decoding and selection circuitry, a matrix of memory cells organized in rows and columns, a sense amplifier circuit, a circuit for storing extracted data and an output buffer which is controlled through an enabling line connected to said control circuitry, each of said decoding and selection circuitry, said memory matrix, and said sense amplifier circuit having a respective propagation delay for a signal therethrough, further comprising:
-
a transition detecting circuit, functionally connected to said input circuitry and capable of generating on an output a pulse for any signal transition detected in said input circuitry; a dummy circuit chain, capable of replicating said respective propagation delays of a signal through said decoding and selection circuitry, said memory matrix, and said sense amplifier circuit and consisting of substantially homologous circuits connected in cascade and individually enableable by means of a reset signal, having an input connected to the output of said detecting circuit and an output; a one shot pulse generating circuit having an input connected to the output of said dummy chain and an output connected to an enabling input of said extracted data storing circuit; a reset signal generating circuit having a first input connected to the output of said one-shot pulse generating circuit, a second input connected to the output of said transition detecting circuit and an output connected to a reset terminal of said homologous circuits of said dummy circuit chain and a reset terminal of said one-shot pulse generating circuit; the device preventing any modification of a data output value of said extracted data storage circuit for any transition of signals occurring after an interval of time following a first transition in said input circuitry, as detected by said detecting circuit, which is shorter than the propagation time of a pulse through said dummy circuit chain. - View Dependent Claims (4)
-
-
5. A memory device having a memory chain including an input address circuitry, memory selection circuitry, memory cell circuitry and memory sense amplifier circuitry, and memory output circuitry, each of the memory circuitries being organized in cascade and having a propagation delay time for a signal propagating therethrough further comprising:
-
a transition detecting circuitry, functionally connected to said input address circuitry and capable of generating an output pulse for an address signal transition detected in said input address circuitry; a dummy circuit chain, capable of replicating a similar propagation delay as a signal through said memory selection circuitry, said memory cell circuitry, and said sense amplifier circuitry, the dummy circuit chain including a plurality of circuits connected in cascade including a dummy selection circuitry, a dummy memory cell circuitry, and a dummy sense amplifier circuitry, each dummy circuitry individually having a delay that is similar to the delay of the corresponding memory circuitry; and an enable signal generating circuit having an input functionally connected to the output of said dummy circuit chain and an output connected to an enabling input of said memory output circuitry for enabling the memory output circuitry to output sensed memory data from said memory sense amplifier circuitry only when enabled via the enable signal generating circuit from the dummy circuit chain. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A memory device having a memory chain including an input address circuitry, memory selection circuitry, memory cell circuitry, memory sense amplifier circuitry, and memory output circuitry, each of the memory circuitries being organized in cascade and having a propagation delay time for a signal propagating therethrough, further comprising:
-
a transition detecting circuitry, functionally connected to said input address circuitry and capable of generating an output pulse for an address signal transition detected in said input address circuitry; a dummy circuit, capable of replicating a similar propagation delay as a signal through said memory selection circuitry, said memory cell circuitry, and said sense amplifier circuitry, the dummy circuit having a delay that is similar to the delay of the corresponding memory circuit chain; and an enable signal generating circuit having an input functionally connected to the output of said dummy circuit an output connected to an enabling input of said memory output circuitry for enabling the memory output circuitry to output sensed memory data from said memory sense amplifier circuitry only when enabled via the enable signal generating circuit upon receiving a signal from the dummy circuit. - View Dependent Claims (15, 16, 17)
-
Specification