Programmable clock for an analog converter in a data processor and method therefor

• US 5,404,386 A
• Filed: 11/26/1993
• Issued: 04/04/1995
• Est. Priority Date: 11/26/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Campbell, Jules D. Jr., McCollough, Kelvin E., Collins, Colleen M., Harrington, Cheri L.
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US08/157,245
• Time in Patent Office: 494 Days
• Field of Search: 377/42, 377/52, 377/55, 307/265, 307/269
• US Class Current: 377/55
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 5/1502 programmable

Abstract

A data processing system (10) includes a programmable clock signal for an analog converter (28). A duty cycle of the programmable clock signal is programmed by an external user in a prescaler rate selection register (16). A counter subsequently counts for a first period of time corresponding to a phase in which the programmable clock signal is asserted. The counter then counts for a second period of time corresponding to a phase in which the programmable clock signal is negated. By allowing the user to program and modify the duty cycle of the programmable clock signal, the performance of the analog converter (28) may be optimized without constraining the requirements of an external system clock.

Claims

1. A method for providing a programmable clock signal to an analog converter, comprising the steps of:

programming a high time value in a first portion of a register;

programming a low time value in a second portion of the register;

asserting the programmable clock signal;

enabling a counter to count to the high time value;

negating the programmable clock signal when the counter equals the high time value;

enabling the counter to count to the low time value;

asserting the programmable clock signal when the counter equals the low time value;

enabling the analog converter to perform a first operation when the programmable clock signal is asserted; and

enabling the analog converter to perform a second operation when the programmable clock signal is negated.

2. The method of claim 1 wherein the high time value corresponds to a high time period.

3. The method of claim 1 wherein the low time value corresponds to a low time period.

4. The method of claim 1 wherein the first operation is a comparison operation.

5. The method of claim 1 wherein the second operation provides a result at an output of the analog converter.

6. The method of claim 1 wherein the counter is enabled to count using a system clock as a reference clock.

7. The method of claim 1 further comprising the steps of:

programming the register with an add select value;

enabling the programmable clock signal to remain asserted for a preselected number of clock cycles after the counter equals the high time value; and

negating the programmable clock signal after the predetermined number of clock cycle.

8. The method of claim 7 wherein the preselected number of clock cycles is equal to one.

9. The method of claim 1 wherein the high time value corresponds to a low time period and the low time value corresponds to a high time period.

10. A data processing system comprising:

register means for storing a high count value and a low count value;

a counter having a first input coupled to the register means for receiving one of the high count value and the low count value, the counter having a second input for receiving a system clock signal, the counter counting to provide an intermediate count value in response to the system clock signal;

a detect circuit coupled to the counter for receiving the intermediate count value, the detect circuit asserting a detect signal when the count value is equal to a preselected count value;

driver means coupled to the detect circuit for receiving the detect signal, the driver means selectively asserting a converter clock signal in response to the detect signal; and

an analog converter coupled to the driver means for receiving the converter clock signal, the analog converter performing a conversion operation in response to the converter clock signal.

11. The data processing system of claim 10 wherein the analog converter clock signal is asserted until the intermediate value stored in the counter is equal to the high count value.

12. The data processing system of claim 10 wherein the analog converter clock signal is negated until the intermediate value stored in the counter is equal to the low count value.

13. The data processing system of claim 10 wherein the analog converter performs the comparison operation when the analog converter clock signal is asserted.

14. The data processing system of claim 13 wherein the analog converter outputs a result of the comparison operation when the analog converter clock signal is negated.

15. The data processing system of claim 10 wherein the preselected count value is equal to zero.

16. The data processing system of claim 10 wherein the counter decrements the intermediate count value stored therein in response to the system clock signal.