Method and apparatus for transferring data in portable image processing system

• US 5,404,463 A
• Filed: 10/21/1992
• Issued: 04/04/1995
• Est. Priority Date: 05/17/1991
• Status: Expired due to Term

• Current Assignee: Eastman Kodak Company
• Original Assignee: Eastman Kodak Company
• Inventors: McGarvey, James E.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US07/964,507
• Time in Patent Office: 895 Days
• Field of Search: 395/325, 395/250, 395/200, 395/275, 395/425
• US Class Current: 710/308
• CPC Class Codes: G06F 13/4226 with asynchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microprocessor system, including a central processing unit (CPU), data source device and data destination device electrically interconnected by first data bus lines, address bus lines and control bus lines of a system bus, is implemented with a transfer signal control line, and second data bus lines interconnecting the data source and data destination devices for direct background transfer of data between the devices. At least one of the devices includes individually sequentially addressable storage locations, and associated address and count registers. The data source device includes "ready" and "enable output" terminals, and the data destination device includes "ready" and "enable input" terminals, all connected in AND-gate configuration so that the devices are enabled for data transfer through the second data bus lines only when both device "ready" signals and the transfer control signal are all present. A starting address is loaded in the address register and a total data unit count is loaded in the count register using the first data bus lines. The transfer control signal is then given, with the address and count registers incremented after each data unit is transferred. Once the process is started, data is transferred data unit-by-data unit and without the need for direct CPU involvement, in synchronism with the system clock, until the count register indicates completion of transfer of the entire block.

Claims

1. In a microprocessor system comprising a central processing unit (CPU), a memory and another device;

the memory having a plurality of individually addressable data unit storage locations and the other device having at least one individually addressable data unit storage location; and

the CPU, memory and other device being respectively electrically interconnected by a system bus, including a first set of data bus lines, a set of address bus lines and a set of control lines, so that a data unit can be transferred between the memory and the other device under control of the CPU in a process in which the data unit is read from a first addressed one of the storage locations of the memory or other device in accordance with a first address placed on the address bus lines, and then written to a second addressed one of the storage locations of the other device or memory in accordance with a second address placed on the address bus lines;

the improvement comprising;

the system bus further including a second set of data lines interconnecting the memory and the other device;

an address register connected to the first set of data lines for receiving and storing a starting address of sequentially addressable ones of the memory storage locations, and coupled to the memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines;

a count register connected to the first set of data lines for receiving and storing a number corresponding to a total number of data units in a block of data units to be transferred between the sequentially addressable ones of the memory storage locations and the other device at least one storage location;

first "ready" signal means for signalling a first "ready" signal when the memory is ready to participate in a transfer of a data unit between the given memory storage location whose address is loaded in the address register and the second set of data bus lines;

second "ready" signal means for signalling a second "ready" signal when the other device is ready to participate in a transfer of a data unit between the second set of data bus lines and the other device at least one storage location;

transfer control signal means, connected to the CPU, for signalling a transfer control signal;

enabling signal means, connecting the transfer control signal means and the first and second ready signal means, for enabling the memory and other device for participating with the second set of data lines in the transfer of a data unit, when the transfer control signal, the first "ready" signal and the second "ready" signal are all present; and

means connected to the address and count registers for respectively incrementing the address and count stored in those registers in response to transfer of a data unit between the memory and other device over the second set of data lines; and

means, connected to the CPU, for signalling when the count register has been incremented by a number of times corresponding to the total number of data units to be transferred;

whereby a block of data units can be transferred between the sequentially addressable ones of the memory storage locations and the other device at least one storage location through the second set of data lines, data unit-by-data unit, under control of the enabling signal means.

2. An improvement as in claim 1, wherein the enabling signal means comprises a hard-wired AND-gate connection between the transfer control signal means, the first "ready" signal means, and the second "ready" signal means.

3. An improvement as in claim 2, wherein the transfer control signal means comprises a transfer control signal line;

wherein the first "ready" signal means comprises the memory having a first "ready" signal terminal;

the second "ready" signal means comprises the other device having a second "ready" signal terminal; and

wherein the AND-gate connection comprises the memory having a first "enable" signal terminal connected to the transfer control signal line, the other device having a second "enable" signal terminal connected to the transfer control signal line, a first diode connected between the first "ready" signal terminal and the first "enable" signal terminal, and a second diode connected between the second "ready" signal terminal and the second "enable" signal terminal.

4. An improvement as in claim 1, wherein the other device is an input/output port circuit.

5. An improvement as in claim 1, wherein the other device is another memory;

the other device at least one storage location is another plurality of individually addressable data unit storage locations; and

the system further comprises another address register connected to the first set of data lines for receiving and storing another starting address of sequentially addressable ones of the other memory storage locations, and coupled to the other memory for specifying the address of a given memory storage location to be in data transfer communication with the second set of data bus lines; and

means connected to the other address register for incrementing the address stored in the other address register in response to transfer of a data unit between the memory and other device over the second set of data lines.

6. An improvement as in claim 1, wherein the microprocessor system further comprises a system clock;

and wherein the enabling signal means further comprises means for enabling the memory and other device in synchronism with the system clock.

7. A microprocessor system suitable for the transfer of a block of image data units, comprising:

a central processing unit (CPU);

a data source device;

a data destination device;

at least one of the data source and data destination devices including a plurality of individually addressable data unit storage locations;

a system bus, including a first set of data bus lines, a set of address bus lines, a set of control bus lines, electrically interconnecting the CPU, data source device and data destination device;

a second set of data bus lines interconnecting the data source and data destination devices; and

a transfer control signal line;

an address register connected to the first set of data lines for receiving a starting address of sequentially addressable ones of the plurality of storage locations, and connected to specify a given one of the sequentially addressable ones of the storage location to be in data transfer communication with the second set of data bus lines;

first "ready" signal means coupled to the data source device for signalling when the data source device is ready to transfer data to the second set of data bus lines;

second "ready" signal means associated with the data destination device for signalling when the data destination device is ready to transfer data from the second set of data bus lines;

means for delivering a transfer control signal to the transfer control signal line from the CPU;

enabling means, connecting the transfer control signal line to the first and second "ready" signal means, for enabling the data source device to transfer a data unit to the data destination device through the second set of data bus lines in response to the simultaneous occurrence of the first "ready" signal, the second "ready" signal and the transfer control signal;

means connected to the address register for incrementing the address stored in that register in response to transfer of a data unit from the data source to the data destination device; and

means for signalling when all data units in the block have been transferred.

8. A microprocessor system an in claim 7, wherein the means for signalling when all data units in the block have been transferred comprises a count register connected to the first set of data bus lines for receiving and storing a number corresponding to a total number of data units in the block of data units to be transferred;

means connected to the count register for incrementing the number stored in the count register in response to transfer of a data unit from the data source to the data destination device; and

means, connected to the CPU, for signalling when the count register has been incremented by a number of times corresponding to the total number of data units to be transferred.

9. A system as in claim 7, wherein the data source device comprises a random access memory.

10. A system as in claim 9, wherein the data destination device comprises a small computer system interface (SCSI) input/output port circuit.

11. A system as in claim 7, further comprising a system clock;

and wherein the enabling means further comprises means for enabling the transfer of data in synchronism with the system clock.

12. A system as in claim 7, wherein the enabling means comprises a hard-wired AND-gate connection between the transfer control signal line, the first "ready" signal means, and the second "ready" signal means.

13. A system as in claim 12, wherein the first "ready" signal means comprises the data source device having a first "ready" signal terminal;

the second "ready" signal means comprises the data destination device having a second "ready" signal terminal; and

wherein the AND-gate connection comprises the source device having a first "enable" signal terminal connected to the transfer control signal line, the data destination device having a second "enable" signal terminal connected to the transfer control signal line, a first diode connected between the first "ready" signal terminal and the first "enable" signal terminal, and a second diode connected between the second "ready" signal terminal and the second "enable" signal terminal.

14. In a microprocessor system comprising a central processing unit (CPU), a memory and another device;

the memory having a plurality of individually addressable data unit storage locations and the other device having at least one individually addressable data unit storage location; and

the CPU, memory and other device being respectively electrically interconnected by a system bus, including a first set of data bus lines, a set of address bus lines and a set of control lines, so that a data unit can be transferred between the memory and the other device under control of the CPU in a process in which the data unit is read from a first addressed one of the storage locations of the memory or other device in accordance with a first address placed on the address bus lines, and then written to a second addressed one of the storage locations of the other device or memory in accordance with a second address placed on the address bus lines;

the method of transferring a block of data units between sequentially addressed ones of the memory storage locations and the other device at least one storage location, the method comprising the steps of;

providing a second set of data bus lines connecting the memory and the other device;

using the first set of data bus lines, loading a starting address of the sequentially addressed ones of the memory storage locations into an address register;

using the first set of data bus lines, loading a number corresponding to a total number of data units in the block into a count register;

signalling a transfer control signal when the starting address and total number count have been loaded;

signalling a first "ready" signal when the memory is ready to participate in a data unit transfer;

signalling a second "ready" signal when the other device is ready to participate in a data unit transfer;

in response to the simultaneous presence of all of the transfer control signal, first "ready" signal and second "ready" signal, enabling the transfer of a data unit between the memory storage location whose address is present in the address register and the at least one storage location, through the second set of data bus lines;

incrementing the contents of the address and count registers; and

repeating the enabling and incrementing steps until the contents of the count register indicates that the total number of data units in the block has been transferred.

15. A method as in claim 14, wherein the enabling step occurs in synchronism with timing pulses of a system clock.

16. The method as in claim 14, wherein the other device is another memory;

the other device at least one storage location is another plurality of individually addressable data unit storage locations;

the method further comprises the step of using the first set of data bus lines, loading another starting address of sequentially addressable ones of the other memory storage locations into another address register;

the enabling step comprises transferring the data unit between the memory storage location whose address is present in the address register and the other memory storage location whose address is present in the other address register; and

the incrementing step further comprises also incrementing the contents of the other address register.

17. A method for transferring a block of image data units, between a data source device and a data destination device of a microprocessor system, at least one of the data source and data destination devices including a plurality of individually addressable data unit storage locations;

the system including a central processing unit (CPU), and a system bus having a first set of data bus lines, a set of address bus lines and a set of control bus lines electrically interconnecting the CPU, data source device and data destination device; and

the data source device and data destination device each including a "ready" terminal for indicating a data transfer "ready" status;

the method comprising;

providing a second set of data bus lines electrically connecting the data source and data destination devices; and

a transfer control signal line for signalling a transfer control signal;

providing the data source device with an "enable output" terminal for receiving an "enable" signal to enable data transfer from the data source device to the second set of data bus lines; and

the data destination device with an "enable input" terminal for receiving an "enable" signal to enable data transfer from the second set of data bus lines to the data destination device; and

connecting the "ready," "enable output" and "enable input" terminals in an AND-gate arrangement to the transfer control line, so that the "enable" signals will be given only when "ready" signals are present at both "ready" terminals and the transfer control signal is present at the transfer control line.

18. A method as in claim 17, further comprising the steps of loading a starting address of sequentially addressable ones of the plurality of storage locations into an address register;

signalling a transfer control signal on the transfer control line; and

incrementing the contents of the address register after each occurrence of the "enable" signals.

19. A method as in claim 18, further comprising the steps of loading a number corresponding to a total number of data units in the block into a count register;

incrementing the contents of the count register after each occurrence of the "enable" signals.

20. A method as in claim 19, wherein the system has a system clock and data units are transferred in synchronism with the system clock.