Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
First Claim
1. A method of operating a first processor in a multi-processor digital computer system having said first processor, a second processor, and a system memory accessed by both of said first and second processors over a system bus operating in accordance with a block ownership cache coherency protocol, said first processor having a cache memory for storing blocks of data in association with memory addresses, said method comprising the steps of:
- a) fetching data having a specified memory address for a data processing operation by searching said cache memory for said specified memory address, and when said specified memory address is not found in said cache memory, storing the specified memory address in a content addressable memory, and sending a fill data request including said specified memory address to the system memory;
b) before receipt of fill data from the system memory,i) receiving a cache coherency request from said second processor in accordance with said block ownership cache coherency protocol, said cache coherency request including said specified memory address and requesting invalidation of a block of data having the specified memory address, andii) checking whether said specified memory address is stored in said content addressable memory, delaying execution of said cache coherency request until said fill data is received from said system memory; and
c) receiving said fill data from said system memory, and using said fill data for said data processing without retaining a validated block of said fill data in said cache memory.
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Accused Products
Abstract
A processor and method for delaying the processing of cache coherency transactions during outstanding cache fills in a multi-processor system using a shared memory. A first processor fetches data having a specified address by addressing a cache memory, and when the specified address is not in the cache, saving the specified address in a fill address memory, and sending a fill request to the shared memory. Before return of fill data, the first processor receives a cache coherency request including the specified address from a second processor requesting invalidation of an addressed block of data. The first processor responds by checking whether the fill address memory includes the specified address, and upon finding the specified address in the fill address memory, delaying execution of the cache coherency request until the fill data is returned, and when the fill data is returned, using the fill data without retaining a validated block of the fill data in the cache. In a preferred embodiment, the fill memory is a content-addressable memory including a plurality of entries, and each entry has a fill address, an ownership fill bit (OREAD), an ownership-read invalidate pending bit (OIP), and a read invalidate pending bit (RIP). The OIP or RIP bit is set when execution of a cache coherency request is delayed, and these bits are read upon completion of a fill to execute the delayed request.
119 Citations
19 Claims
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1. A method of operating a first processor in a multi-processor digital computer system having said first processor, a second processor, and a system memory accessed by both of said first and second processors over a system bus operating in accordance with a block ownership cache coherency protocol, said first processor having a cache memory for storing blocks of data in association with memory addresses, said method comprising the steps of:
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a) fetching data having a specified memory address for a data processing operation by searching said cache memory for said specified memory address, and when said specified memory address is not found in said cache memory, storing the specified memory address in a content addressable memory, and sending a fill data request including said specified memory address to the system memory; b) before receipt of fill data from the system memory, i) receiving a cache coherency request from said second processor in accordance with said block ownership cache coherency protocol, said cache coherency request including said specified memory address and requesting invalidation of a block of data having the specified memory address, and ii) checking whether said specified memory address is stored in said content addressable memory, delaying execution of said cache coherency request until said fill data is received from said system memory; and c) receiving said fill data from said system memory, and using said fill data for said data processing without retaining a validated block of said fill data in said cache memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of operating a first processor in a multi-processor digital computer system having said first processor, a second processor, and a system memory accessed by both of said first and second processors over a system bus operating in accordance with a block ownership cache coherency protocol, said first processor having a cache memory for storing blocks of data and a memory address associated with each of said blocks of data, said method comprising the steps of:
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a) fetching data having a specified memory address for a data processing operation by said first processor by searching said cache memory for said specified memory address, and when said specified memory address is not found in said cache memory, storing the specified memory address in an entry of a content addressable memory having a plurality of entries, and sending a fill data request including said specified memory address to said system memory; b) before receipt of fill data from the system memory, i) receiving a cache coherency request from said second processor in accordance with said block ownership cache coherency protocol, said cache coherency request including said specified memory address, and ii) addressing said content addressable memory with the specified memory address of said cache coherency request, and upon finding that the specified memory address of said cache coherency request is in said entry of said content addressable memory, setting in said content addressable memory an indication that said cache coherency request is pending for said specified memory address; and c) receiving said fill data from said system memory, using said fill data for said data processing operation by said first processor, checking said entry of said content addressable memory for said indication that said cache coherency request is pending for said specified memory address, executing said cache coherency request. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A processor for a multi-processor computer system, said multi-processor computer system having a system bus for coupling processors to a system memory, said system bus operating in accordance with a block ownership cache coherency protocol, said processor comprising, in combination:
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instruction decoding means for decoding computer program instructions to generate requests for reading data at specified read addresses; instruction execution means connected to said instruction means for executing the computer program instructions decoded by said instruction decoding means to generate requests for writing data at specified write addresses; a cache memory for storing blocks of data, and in association with each block of data, a memory address, an indication of whether each block is valid for providing data from said memory address in response to said requests for reading data, and an indication of whether each block is valid for receiving data from said requests for writing data to said memory address; a content addressable memory including a plurality of entries and means for storing in each entry a fill address of a fill request to a system memory in said multi-processor system requesting fill data from said fill address in said shared memory, an indication of whether the fill address is associated with a request for validation for writing data to said fill address, an indication of whether a read invalidate request was received, before return of said fill data, from another processor in said multi-processor system requesting invalidation of any indication that a cache block having said fill address in said cache memory is valid for receiving write data of whether an ownership-read invalidate request was received, before return of said fill data, from another processor in said multi-processor system requesting invalidation of any indication that a cache block having said fill address is valid for providing read data; means, responsive to a request for reading data from a specified read address, for addressing said cache memory with said read address, for reading data from said cache memory when said cache memory contains a cache block having said read address and indicated as valid for providing read data, and when said cache memory does not contain a cache block having said read address and indicated as valid for providing read data, for sending a fill request to said main memory including said read address and for storing said read address in said content addressable memory; means, responsive to a request for writing data to a specified write address, for writing data to said cache memory when said cache memory contains a cache block having said write address and indicated as valid for receiving write data, and when said cache memory does not contain a cache block having said write address and indicated as valid for receiving write data, for sending a fill request to said system memory including said write address and a request for validation for a write operation, and for storing in said content addressable memory said write address together with an indication that the fill address is associated with a request for validation for a write operation; means, responsive to receiving from another processor in said multi-processor system a read invalidate request having a specified read invalidate address, for addressing said content addressable memory with said specified read invalidate address, and when a fill address matching said specified read invalidate address is found in said content addressable memory, for setting the indication of whether a read invalidate request was received from another processor in said multi-processor system before return of said fill data; means, responsive to receiving from another processor in said multi-processor system an ownership-read invalidate request having a specified ownership-read invalidate address, for addressing said content addressable memory with said specified ownership-read invalidate address, and when a fill address matching said specified ownership-read invalidating address is found in said content addressable memory, for setting the indication of whether an ownership-read invalidate request was received from another processor in said multi-processor system before return of said fill data; first means, responsive to return of said fill data for checking said indication in said content addressable memory of whether an ownership-read invalidate request was received before return of said fill data, and when an ownership-read invalidate request was received before return of said fill data, for invalidating an indication that a cache block having the fill address in said cache memory is valid for providing read data; and
second means, responsive to return of said fill data, for checking the indication in said content addressable memory of whether a read invalidate request was received before return of said fill data, and when a read invalidate request was received before return of said fill data, for invalidating an indication that a cache block having the fill address in said cache memory is valid for receiving write data. - View Dependent Claims (17, 18, 19)
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Specification