BIOS independent power management for portable computer

• US 5,404,546 A
• Filed: 02/16/1993
• Issued: 04/04/1995
• Est. Priority Date: 02/14/1991
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell Inc. (Dell Technologies Inc.)
• Inventors: Stewart, Gregory N.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/017,581
• Time in Patent Office: 777 Days
• Field of Search: 395/750, 395/575, 395/325, 364/273.1, 364/DIG. 1, 364/948.8, 364/DIG. 2, 364/707
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/325 Power saving in peripheral device

Abstract

Method and apparatus for effecting BIOS independent power management of a personal computer system having a processor complex connected via a system bus to at least one I/O device capable of operating in a reduced power consumption state. A power control system comprising a dedicated power management microcontroller monitors the activity of various I/O devices. When a particular device or combination of devices has remained inactive for the preselected time interval, the power control system issues a bus request to a processor complex. When the processor complex acknowledges the bus request, the power control system asserts control as master of the system bus and performs the operations necessary to cause at least one device to enter a reduced power consumption state. The power control system then surrenders control of the bus to the processor complex. In one aspect, a CPU clock controller is utilized to reduce the processing speed of the processor complex CPU.

Claims

1. A method for controlling power consumption of a personal computer system, the system including a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, said complex and said devices being interconnected by a system bus, the method comprising:

monitoring, by a power control system, said computer system for I/O activity associated with at least one said device;

setting a timer for a predetermined interval;

resetting said timer to said predetermined interval upon detecting said I/O activity responsive to said monitoring;

said power control system issuing a bus request signal to said complex upon elapse of said predetermined interval for gaining control of said bus as master independent of said complex; and

said power control system generating signals as master of said bus independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state.

2. The method of claim 1 further comprising:

said power control system deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said signal generation.

3. The method of claim 1 further comprising:

monitoring said computer system for I/O activity when said at least one device is operating in said reduced power consumption state;

said power control system issuing a bus request signal to said complex to gain control of said bus as master when said I/O activity is detected in response to said reduced power consumption state monitoring; and

said power control system generating signals on said bus as master independent of said complex to said at least one device for removing said at least one device from said reduced power consumption state.

4. The method of claim 3 further comprising:

said power control system deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said removal signal generation.

5. The method of claim 1 wherein said processor complex includes a central processing unit (CPU) and a CPU clock controller connected to said bus, the method further comprising said power control system generating signals on said system bus as master independent of said complex to said CPU clock controller for reducing the processing speed of said CPU.

6. The method of claim 5 wherein said CPU processing speed is reduced to 0 megahertz.

7. The method of claim 5 wherein said CPU processing speed is reduced to 3.125 megahertz.

8. The method of claim 1 wherein said predetermined interval is a default interval for each said at least one device.

9. The method of claim 1 wherein said predetermined interval is a user selected interval for each said at least one device.

10. The method of claim 1 wherein said at least one device comprises a display having a back light and a hard disk having a drive motor, the signal generating step further comprising:

generating signals for turning off said display back light; and

generating signals for turning off said drive motor.

11. A method for controlling power consumption of a personal computer system, the computer system including a processor complex having a central processing unit (CPU), a CPU clock controller and input/output (I/O) devices each capable of operating in a reduced power consumption state, said complex, said controller and said devices being interconnected by a system bus, the method comprising:

monitoring, by a power control system, said computer system for I/O activity associated with at least one said device;

setting a timer for a predetermined interval;

resetting said timer to said predetermined interval upon detecting said I/O activity responsive to said monitoring;

said power control system issuing a bus request signal to said complex upon elapse of said predetermined interval for gaining control of said bus as master independent of said complex;

said power control system generating signals on said bus as master independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state;

said power control system generating signals on said bus as master independent of said complex to said CPU clock controller for reducing the processing speed of said CPU;

said power control system deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said signal generation;

said power control system monitoring said computer system for I/O activity when said at least one device is in said reduced power consumption state;

said power control system issuing a bus request signal to said complex to gain control of said bus as master when said I/O activity is detected in response to said reduced power consumption state monitoring;

said power control system generating signals on said bus as master independent of said complex to said controller and said at least one device for removing said CPU from said reduced speed and for removing said at least one device from said reduced power consumption state; and

said power control system deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said removal signal generation.

12. A microcontroller connected to a system bus of a personal computer system, said microcontroller for managing power consumption of the system, the system including on said system bus a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, the microcontroller comprising:

at least one signal line connected to at least one said device for receiving signals indicative of I/O activity of said at least one device;

at least one control line connected to said complex for granting and relinquishing said microcontroller control of said system bus as master;

logic for monitoring said at least one signal line for said signals indicative of said I/O activity;

logic for setting a timer for a predetermined interval;

logic for resetting said timer for said predetermined interval in the presence of said I/O activity responsive to said monitoring;

logic for issuing a bus request signal on said at least one control line to said complex upon elapse of said interval to gain control of said bus as a master independent of said complex;

logic for generating signals on said bus as master independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state; and

logic for deasserting said bus request signal on said at least one control line to said complex for releasing control of said bus as master upon completion of said signal generation.

13. The microcontroller of claim 12 wherein said processor complex includes a central processing unit (CPU), said microcontroller further comprising:

a CPU clock controller connected to said system bus;

logic for generating signals on said system bus as master independent of said complex to said CPU clock controller for reducing the processing speed of said CPU.

14. The microcontroller of claim 13 wherein said CPU processing speed is reduced to 0 megahertz.

15. The microcontroller of claim 13 wherein said CPU processing speed is reduced to 3.125 megahertz.

16. The microcontroller of claim 12 wherein said predetermined value is a default value.

17. The microcontroller of claim 12 wherein said predetermined interval is a user selected interval for each said at least one device.

18. The microcontroller of claim 12 further comprising:

logic for monitoring said at least one signal line for said signals indicative of said I/O activity when said at least one device is in said reduced power consumption state;

logic for issuing a bus request signal on said at least one control line to said complex to gain control of said bus as master when said I/O activity is detected in response to said reduced power consumption state monitoring;

logic for generating signals on said bus as master independent of said complex to said at least one device for removing said at least one device from said reduced power consumption state; and

logic for reasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said removal signal generation.

19. A microcontroller connected to a system bus of a personal computer system, said microcontroller for managing power consumption of the system, the system including on said system bus a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, the microcontroller comprising:

at least one signal line connected to at least one of said devices for receiving signals indicative of I/O activity of said at least one device;

at least one control line connected to said complex for granting and relinquishing said microcontroller control of said system bus as master;

logic for monitoring said at least one signal line for said signals indicative of said I/O activity;

logic for setting a timer for a predetermined interval;

logic for resetting said timer for said predetermined interval in the presence of said I/O activity responsive to said monitoring;

logic for issuing a bus request signal on said at least one control line to said complex upon elapse of said interval to gain control of said bus as a master independent of said complex;

logic for generating signals on said bus as master independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state;

logic for deasserting said bus request signal on said at least one control line to said complex for releasing control of said bus as master upon completion of said signal generation;

logic for monitoring said at least one signal line for said signals indicative of said I/O activity when said at least one device is in said reduced power consumption state;

logic for issuing a bus request signal on said at least one control line to said complex to gain control of said bus as master when said I/O activity is detected in response to said reduced power consumption state monitoring;

logic for generating signals on said bus as master independent of said complex to said at least one device for removing said at least one device from said reduced power consumption state; and

logic for deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said removal signal generation.

20. The microcontroller of claim 19 wherein said processor complex includes a central processing unit (CPU), said microcontroller further comprising:

a CPU clock controller connected to said system bus;

logic for generating signals on said system bus as master independent of said complex to said CPU clock controller for reducing the processing speed of said CPU.

21. The microcontroller of claim 20 wherein said CPU processing speed is reduced to 0 megahertz.

22. The microcontroller of claim 20 wherein said CPU processing speed is reduced to 3.125 megahertz.

23. The microcontroller of claim 19 wherein said predetermined value is a default value.

24. The microcontroller of claim 19 wherein said predetermined interval is a user selected interval for each said at least one device.

25. A method for controlling power consumption of a personal computer system, the system including a processor complex and input/output (I/O) devices capable of operating in a reduced power consumption state, said complex and said devices being interconnected by a system bus, the method comprising:

monitoring, by a power control system, said computer system for I/O activity associated with at least one said device;

setting a timer for a predetermined interval according to a user selected interval for said at least one device;

resetting said timer to said predetermined interval upon detecting said I/O activity responsive to said monitoring;

said power control system issuing a bus request signal to said complex upon elapse of said predetermined interval for gaining control of said bus as master independent of said complex; and

said power control system generating signals as master of said bus independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state.

26. The method of claim 25 wherein said at least one device comprises a display having a back light and a hard disk having a drive motor, the signal generating step further comprising:

generating signals for turning off said display back light; and

generating signals for turning off said drive motor.