System for storing different categories of routines in internal and external memories respectively and executing the routines based upon impact by generated noise

• US 5,404,547 A
• Filed: 04/29/1992
• Issued: 04/04/1995
• Est. Priority Date: 04/30/1991
• Status: Expired due to Fees

• Current Assignee: Motorola Israel Limited (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Newman, Yona, Koren, Victor, Diamantstein, Menachem
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Kim, Sang Hui
• Application Number:
  US07/875,930
• Time in Patent Office: 1,070 Days
• Field of Search: 342/195, 342/198, 342/202, 342/203, 395/375, 395/775, 395/800, 395/650, 395/575, 395/775, 395/700
• US Class Current: 455/73
• CPC Class Codes: H04B 1/40 Circuits

Abstract

This invention relates to electronic equipment comprising microprocessors, and more specifically microprocessors employed within radio receiver circuits, incorporating on-chip memory (301, 302, 303) and which have the ability to operate in either a single chip or expanded mode. The single chip mode restricts microprocessor (300) operation to internal operation and thereby inhibits external addressing and locally generated noise whereas the expanded mode allows external addressing. A software program, comprised from modules of program code, is categorised into a first and a second category of routines. First category routines are related to equipment functions which are affected by generated noise to a higher degree and, when in operation, are stored in the internal memory (301, 302, 303). Second category routines are stored in a memory external to the microprocessor (201, 202) and are related to equipment functions which are affected by generated noise to a lesser degree. The first and second category routines are executed in the microprocessor'"'"'s single chip and expanded modes respectively.

Claims

1. Electronic equipment comprising:

a) a microprocessor, for the processing and output of data signals, having;

i) internal memory

ii) a central processing unit; and

iii) internal buses coupled between said memory and said processing unit;

b) memory external to said microprocessor; and

c) external buses, for external addressing, coupled between said memory external to said microprocessor and said microprocessor;

d) first portion susceptible to generated noise to a higher degree and second portion susceptible to generated noise to a lesser degree;

wherein the microprocessor has the ability to operate in;

i) a single chip mode in which the microprocessor restricts itself to internal operation between said internal memory, said processing unit and said internal buses and thereby inhibits addressing on the external buses and reduces locally generated noise; and

ii) an expanded mode in which the microprocessor performs operations on the external bus;

the equipment further comprising;

e) a software program associated therewith, comprised from modules of program code, and categorized into;

i) a first category of routines for execution by the microprocessor in single chip mode, stored in said internal memory, and related to first portion functions affected by generated noise to a higher degree; and

ii) a second category of routines for execution by the microprocessor in expanded mode, stored in said memory external to the microprocessor, and related to second portion functions affected by generated noise to a lesser degree; and

f) means for executing the first category routines in the microprocessor'"'"'s single chip mode for controlling said first portion and executing the second category routines in the microprocessor'"'"'s expanded mode for controlling said second portion.

2. Electronic equipment in accordance with claim 1, wherein the first category of routines are further sub-divided into:

a) a set of primary first category algorithms comprising modules of first category code which are continually operational and which are permanently stored within the internal memory of said microprocessor; and

b) a set of secondary first category algorithms comprising modules of first category code which are only executed from time to time and which are initially stored in the memory external to said microprocessor;

wherein the electronic equipment further comprises means for loading the secondary first category routines into the internal memory of the microprocessor when called upon to implement such.

3. Electronic equipment according to claim 2, further comprising:

input means for receiving a command to change between said single chip and said expanded mode; and

means for implementing a mode change in response to said received command;

whereby the command to change between said modes forces a micro-reset of the microprocessor.

4. Electronic equipment according to claim 3, wherein

the means for implementing the change between modes comprises storage means receptive to a bit value, generated by the microprocessor, which represents a vector signifying a desired start location within the software program for the new operating mode, such that

the bit value is written to the storage means prior to the forced micro-reset and is read from the storage means immediately after the mode change has occurred.

5. Electronic equipment according to claim 4, wherein means are provided for

writing the vector, representing a desired start location for the new operating mode, to the internal memory of the microprocessor prior to the initialization of the forced micro-reset and then immediately reading the vector after the change of mode has occurred.

6. Electronic equipment according to claim 5, wherein the command to change between said modes is generated in response to

the registration of a clock monitor fail within the microprocessor and the issuance of a STOP instruction by a module of code.

7. Electronic equipment according to claim 5, wherein the command to change between said modes is generated in response to

the enablement of a watchdog timer circuit and the prevention of a software reset of the watchdog timer.

8. Electronic equipment according to claim 5, wherein the command to change between said modes is generated in response to

the detection of an illegal op-code at a specific, designated location within a module of code.

9. Electronic equipment according to claim 5, wherein the command to change between said modes is generated in response to

the initialization of a mode select means and the activation of a coupled microprocessor reset input means.

10. Electronic equipment according to claims 4, wherein

the vector is uniquely defined by the command received from each specific input means.

11. Electronic equipment according to claim 10, wherein

the vector contains a routine which accesses a first module of code which re-initiates the microprocessor and then initiates a desired second module of code.

12. Electronic equipment in accordance with claim 1, wherein the internal memory comprises both volatile and non-volatile memory.

13. Electronic equipment according to claim 1, wherein

the microprocessor forms part of radio communications apparatus comprising:

a receiver;

a transmitter; and

a user interface.

14. A method for reducing the effect of locally generated noise in electronic equipment having first portion susceptible to generated noise to a high degree, second portion susceptible to generated noise to a lesser, a microprocessor, memory external to said microprocessor, and external buses, for external addressing, coupled between said memory external to said microprocessor and said microprocessor, said microprocessor having internal memory, a central processing unit and internal buses coupled between said memory and said processing unit;

the method comprising the steps of;

a) providing modules of program code;

b) partitioning said modules of program code into;

i) first category routines which, are related to first portion functions affected by generated noise to a higher degree; and

ii) second category routines which, when in operation are related to second portion functions affected by generated noise to a lesser degree;

c) storing at least temporaneously the first category routines in memory internal to said microprocessor;

d) storing the second category routines in memory external to said microprocessor;

e) operating said microprocessor selectively in single chip mode in which the microprocessor restricts itself to internal operation between said internal memory, said processing unit and said internal buses and thereby inhibits addressing on the external buses and reduces locally generated noise; and

in an expanded mode in which the microprocessor performs operation on the external bus;

f) executing said first category routines for controlling said first portion whilst said microprocessor is operating in said single chip mode; and

g) executing said second category routines for controlling said second portion whilst said microprocessor is operating in said expanded mode;

whereby the detrimental affect of locally generated noise on equipment functions, susceptible to said noise to a higher degree, is reduced.

15. A method in accordance with claim 14, further comprising the steps of:

(f) sub-dividing the first category routines into;

i) a set of primary first category algorithms comprising modules of first category code which are continually operational and which are permanently stored within the internal memory of said microprocessor; and

ii) a set of secondary first category algorithms comprising modules of first category code which are only executed from time to time and which are initially stored in the memory external to said microprocessor; and

g) having the microprocessor execute the primary first category algorithms in said single chip mode.

16. Equipment in accordance with claim 15, further comprising:

input means for receiving an instruction to change between said single chip and said expanded mode; and

loading means for loading the secondary first category routines into the internal memory of the microprocessor in response to said received command;

the method further comprising the steps of;

h) receiving an instruction to change between said single chip and said expanded modes;

i) loading said secondary first category algorithms into said internal memory;

i) entering said single chip mode; and

j) executing said secondary first category algorithms in said single chip mode.

17. A method in accordance with claim 16, wherein the step of changing between said single chip and said expanded modes is implemented through:

k) the forcing of a micro-reset of the microprocessor.

18. A method in accordance with claim 17, further comprising the steps of:

l) storing a bit value, which represents a vector signifying a desired start location within the software program and which is generated by the microprocessor, in said internal memory prior to the initialisation of said forced micro-reset;

m) reading stored bit value immediately after a change between said single chip and said expanded modes; and

n) executing the code located thereat.

19. Electronic equipment comprising:

a) microprocessor which contains on-chip memory and internal buses and which has the ability to operate in a single chip mode and an expanded mode, wherein the single chip mode restricts microprocessor operation to internal operation and thereby inhibits external addressing and locally generated noise and the expanded mode allows external addressing;

b) first portion susceptible to generated noise to a high degree and second portion susceptible to generated noise to a lesser degree;

c) a memory external to the microprocessor and coupled thereto;

d) a software program, associated with said electronic equipment comprised from modules of program code which are categorized into;

i) a first category of routines for execution by the microprocessor in single chip mode, stored in said internal memory, and related to first portion functions affected by generated noise to a higher degree; and

ii) a second category of routines for execution by the microprocessor in expanded mode, stored in memory external to the microprocessor, and related to said second portion functions affected by generated noise to a lesser degree; and

e) means for executing the first category routines in the microprocessor'"'"'s single chip mode for controlling said first portion and executing the second category routines in the microprocessor'"'"'s expanded mode for controlling said second portion.

20. Electronic equipment in accordance with claim 19, wherein the first category of routines are further sub-divided into:

a) a set of primary first category algorithms comprising modules of first category code which are continually operational and which are permanently stored within the internal memory of said microprocessor; and

b) a set of secondary first category algorithms comprising modules of first category code which are only executed from time to time and which are initially stored in the memory external to said microprocessor;

wherein the electronic equipment further comprises means for loading the secondary first category routines into the internal memory of the microprocessor when called upon to implement such.

21. Electronic equipment in accordance with claim 20, wherein

the microprocessor forms part of a radio communications device which comprises:

a receiver;

a transmitter; and

a user interface.

22. Electronic equipment in accordance with claim 20, wherein the internal memory comprises:

a) non-volatile memory in which said primary first category algorithms are stored; and

b) volatile memory in which said secondary first category algorithms are periodically loaded and stored.

23. Electronic equipment according to claim 22, further comprising:

input means for receiving a command to change between operating modes; and

means for implementing an operating mode change in response to the reception of a command from the input means;

whereby the command to change between said modes forces a micro-reset of the microprocessor.

24. Electronic equipment according to claim 23, wherein

the means for implementing the change between modes comprises storage means receptive to a bit value, generated from the microprocessor, which represents a vector signifying a desired start location within the software program for the new operating mode, such that

the bit value is written to the storage means prior to the forced micro-reset and is read from the storage means immediately after the mode change has occurred.

25. Electronic equipment according to claim 24, wherein the command to change between said modes is generated in response to

the registration of a clock monitor fail within the microprocessor (300) and the issuance of a STOP instruction by a module of code.

26. Electronic equipment according to claim 24, wherein the command to change between said modes is generated in response to

the enablement of a watchdog timer circuit and the prevention of a software reset of the watchdog timer.

27. Electronic equipment according to claim 24, wherein the command to change between said modes is generated in response to

the detection of an illegal op-code at a specific, designated location within a module of code.

28. Electronic equipment according to claim 24, wherein the command to change between said modes is generated in response to

the initialisation of a mode select means and the activation of a coupled microprocessor reset input means.

29. Electronic equipment according to claim 23, wherein means are provided for

writing a vector, representing a desired start location for a new operating mode, to the internal volatile memory of the microprocessor prior to the initialization of the forced micro-reset and then immediately reading the vector after the mode change has occurred.

30. Electronic equipment according to claims 29, wherein

the vector is uniquely defined by the command received from each specific input means.

31. Electronic equipment according to claim 30, wherein

the vector contains a routine which accesses a first module of code which re-initiates the microprocessor and then initiates a desired second module of code.

32. A method for reducing the effect of locally generated noise in a radio having radio receiver susceptible to generated noise to a high degree, radio transmitter susceptible to generated noise to a lesser degree, a microprocessor with internal memory, a central processing unit, and internal buses coupled between said memory and said processing unit and having memory external to said microprocessor and external buses, for external addressing coupled between said memory external to said microprocessor and said microprocessor;

method comprising the steps of;

a) providing modules of program code;

b) partitioning said modules of program code into;

i) first category routines which, when in operation are related to radio receiver functions; and

ii) second category routines which, when in operation, are related to radio transmitter functions, radio mode change functions and user interaction functions;

c) storing at least temporaneously the first category routines in memory internal to said microprocessor;

d) storing the second category routines in memory external to said microprocessor;

e) operating said microprocessor selectively in single chip mode in which the microprocessor restricts itself to internal operation between said internal memory, said processing unit and said internal buses and thereby inhibits addressing on the external buses and reduces locally generated noise; and

in an expanded mode in which the microprocessor performs operation on the external bus;

f) executing said first category routines for controlling said radio receiver while said microprocessor is operating in said single chip mode; and

g) executing said second category routines for controlling said radio transmitter while said microprocessor is operating in said expanded mode.

33. A method for reducing the effect of locally generated noise in electronic equipment having first portion susceptible to generated noise to a high degree, second portion susceptible to generated noise to a lesser degree, a microprocessor with internal memory, memory external to said microprocessor, and external buses, for external addressing, coupled between said memory external to said microprocessor and said microprocessor, said microprocessor having internal memory, a central processing unit and internal buses coupled between said memory and said processing unit;

the method comprising the steps of;

a) providing modules of program code

b) partitioning said modules of program code into;

i) first category routines which, when in operation, are related to first portion functions affected by generated noise to a higher degree; and

ii) second category routines which, when in operation are related to second portion functions affected by generated noise to a lesser degree;

c) sub-dividing the first category routines into;

i) primary first category algorithms comprising modules of first category code which are substantially continually operational; and

ii) secondary first category algorithms comprising modules of first category code which are executed from time to time;

d) permanently storing said primary first category algorithms in said internal memory of said microprocessor;

e) initially storing said secondary first category algorithms in said memory external to said microprocessor;

f) storing said second category routines in said memory external to said microprocessor;

g) operating said microprocessor selectively in single chip mode in which the microprocessor restricts itself to internal operation between said internal memory, said processing unit and said internal buses and thereby inhibits addressing on the external buses and reduces locally generated noise; and

in an expanded mode in which the microprocessor performs operation on the external bus;

h) executing said primary first category routines for controlling said first portion while said microprocessor is operating in said single chip mode; and

i) executing said second category routines for controlling said second portion while said microprocessor is operating in said expanded mode; and

j) loading said secondary first category routines into said internal memory and executing said secondary first category routines for controlling said first portion while said microprocessor is operating in said single chip mode.