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Pipeline risc processing unit with improved efficiency when handling data dependency

  • US 5,404,552 A
  • Filed: 12/12/1991
  • Issued: 04/04/1995
  • Est. Priority Date: 03/01/1991
  • Status: Expired due to Fees
First Claim
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1. A pipeline processing apparatus including a plurality of registers and a data memory, comprising:

  • memory access means for accessing the data memory to read data therefrom in response to a load instruction;

    register access means responsive to an operation instruction for reading out data to be processed from said plurality of registers;

    first operation means for performing an operation on data received from said register access means;

    determination means for determining whether said operation instruction has a data dependency on said load instruction;

    first selection means responsive to a result of determination by said determination means for selecting data necessary for an operation according to said operation instruction among the data from said register access means and the data loaded by said memory access means;

    second operation means for performing the operation on data selected by said first selection means;

    second selection means responsive to the result of determination by said determination means for selecting either of an output of said first operation means and an output of said second operation means, thus selected output being written back into a register in said plurality of registers.

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