Pipeline risc processing unit with improved efficiency when handling data dependency

• US 5,404,552 A
• Filed: 12/12/1991
• Issued: 04/04/1995
• Est. Priority Date: 03/01/1991
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ikenaga, Chikako
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US07/805,776
• Time in Patent Office: 1,209 Days
• Field of Search: 395/80, 395/375
• US Class Current: 712/41
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

Source operand data supplied from a register file are held in registers. The data of the registers and load data from a data memory are bypassed and supplied to a selection circuit. An execution stage includes an arithmetic and logic unit for performing an operation on the source operand data and a memory access stage includes an arithmetic and logic unit for performing an operation on data selected by the selection circuit. Selection of the selection circuit is controlled by data dependency between a load instruction and an operation instruction following the same. The output of the arithmetic and logic unit in the execution stage and the output of the arithmetic and logic unit in the memory access stage are selected in a selector according to a presence/absence of data dependency. Load data from the data memory is also supplied to the selector. If an operation instruction supplied following a load instruction uses load data, execution of this operation instruction in the memory access stage eliminates a pipeline stall and the need for inserting a "NOP" instruction for pipeline stall prevention, making it possible for an operational processing unit to operate at a high speed without causing a slot in the pipeline.

Claims

1. A pipeline processing apparatus including a plurality of registers and a data memory, comprising:

memory access means for accessing the data memory to read data therefrom in response to a load instruction;

register access means responsive to an operation instruction for reading out data to be processed from said plurality of registers;

first operation means for performing an operation on data received from said register access means;

determination means for determining whether said operation instruction has a data dependency on said load instruction;

first selection means responsive to a result of determination by said determination means for selecting data necessary for an operation according to said operation instruction among the data from said register access means and the data loaded by said memory access means;

second operation means for performing the operation on data selected by said first selection means;

second selection means responsive to the result of determination by said determination means for selecting either of an output of said first operation means and an output of said second operation means, thus selected output being written back into a register in said plurality of registers.

2. A pipeline processing apparatus according to claim 1, wherein said determination means includes first storage means for storing a first source register operand included in said operation instruction, second storage means for storing a second source register operand in said operation instruction, third storage means for storing a destination register operand included in said load instruction, detection means for detecting coincidence between the operand in said third storage means and one of the operands in said first and second storage means, and control means responsive to an output of said detection means for generating first and second control signals for controlling respective selecting operations of said first and second selection means.

3. A pipeline processing apparatus according to claim 2, wherein said register access means includes means for detecting a load instruction and generating a load indicating signal indicating that a load instruction is to be executed, and wherein said second selection means includes means (FIG. 13) responsive to said second control signal and said load indicating signal, for selecting one of the outputs of the first operation means and the second operation means and the data loaded from said data memory by said memory access means.

4. A pipeline processor including a register file with a plurality of registers, comprising:

an instruction decode stage for decoding an instruction fetched from an instruction memory, said decode stage including register access means for reading data of a register in the register file corresponding to a fetched and decoded instruction, and detection means for detecting an operation instruction to be executed following a load instruction;

an instruction execution stage for performing a predetermined operation on data received from said register access means, and including bypassing means for bypassing the data from said register access means without any arithmetic or logical operation thereon;

determination means responsive to said detection means for determining whether there exists data dependency between said operation instruction and said load instruction;

a memory access stage for accessing a data memory when a load instruction is supplied from said instruction stage, said memory access stage including selection means responsive to said determination means for selectively passing one of the data from said bypassing means and data loaded from said data memory, and another operation means for performing the predetermined operation on data received from said selection means; and

a write back stage for writing data into a register in the register file, said write back stage including another selection means responsive to said determination means for selectively passing one of the outputs of the operation means and the another operation means, for the writing back into a register of the register file.

5. A pipeline processor according to claim 4, wherein said another selection means further includes means (FIG. 13) responsive to said detection means and said determination means for selectively passing one of the outputs of the operation means and the another operation means and the data loaded from said data memory.

6. A pipeline processor according to claim 4, wherein said determination means includes first means for detecting that a destination register indicated by said load instruction is the same as a source register indicated by said operation instruction, second means responsive to said first means for generating a first control signal for controlling a selection operation of said selection means and a second control signal for controlling a selection operation of said another selection means.

7. A pipeline processor according to claim 6, wherein said determination means further includes delay means for delaying said second control signal to adjust the timing of the selection of said another selection means to an operation timing to said memory access stage.

8. A method of executing an instruction comprising the steps of:

decoding an instruction fetched from an instruction memory, and reading data of a corresponding register of a register file;

performing an operation on data read out from the corresponding register;

bypassing the data read out from the corresponding register;

detecting that a currently executed instruction is an operation instruction immediately following a load instruction and having data dependency thereon;

accessing a data memory in response to the load instruction for reading out data designated by the load instruction therefrom;

bypassing data read out and loaded from the data memory;

selectively passing the data read out from the corresponding register and the data read out and loaded from the data memory to provide data necessary for execution of said operation in response to the result of the detection in said step of detecting;

performing said operation on the data thus selectively passed; and

further selectively passing the result of operation on the data from the corresponding register and the result of operation on the data thus selectively passed in response to the result of the detection in said step of detecting.

9. A method of executing an instruction according to claim 8, wherein the data from the corresponding register includes data from two different registers, and wherein said step of selectively passing includes the step of selecting one of the data from the two different registers, and the data read out and loaded from the data memory, when the result of the detection in said step of detecting indicates that the operation instruction utilizes the data loaded from the data memory in response to the load instruction.

10. A method of executing an instruction according to claim 8, further including the steps of:

detecting a load instruction for generating a load indicating signal; and

selecting one among the result of operation on the data of the corresponding register, the result of operation on thus selectively passing data and the data read out and loaded from the data memory in response to the load indicating signal and the result of the detection in said step of detecting.