Stress sensitive P-N junction devices formed from porous silicon and methods for producing the same

• US 5,405,786 A
• Filed: 04/29/1994
• Issued: 04/11/1995
• Est. Priority Date: 12/16/1993
• Status: Expired due to Term

• Current Assignee: Kulite Semiconductor Products Inc
• Original Assignee: Kulite Semiconductor Products Inc
• Inventors: Kurtz, Anthony D.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MULPURI, SAVITRI
• Application Number:
  US08/237,011
• Time in Patent Office: 347 Days
• Field of Search: 437/15, 437/71, 437/901, 437/974, 148/DIG. 1 L, 148/DIG. 159, 257/417
• US Class Current: 438/53
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: Y10S 438/96 Porous semiconductor

Abstract

Stress sensitive P-N junction devices are fabricated by forming a porous layer in a semiconductor of a given conductivity, diffusing dopants of the opposite conductivity into the porous layer and forming a non-porous layer on the porous layer. This results in a microporous structure having a plurality of microcrystalline regions extending therethrough, which enhances the quantum confinement of energetic carriers and results in a device which is highly sensitive to stress.

Claims

1. A method of fabricating a stress sensitive semiconductor device comprising the steps of:

providing a first substrate of a semiconductor material having a given conductivity;

forming a porous region on said first substrate, said porous region being of said given conductivity;

doping said porous region to a depth with a dopant having a conductivity opposite to said given conductivity, wherein said selected depth of said porous region having said dopant and said porous region forms an array of p-n junctions extending therethrough; and

growing a layer of said semiconducting material on said porous region, said layer being of said conductivity opposite to said given conductivity, wherein said porous region, said selected depth of said porous region having said dopant and said layer form a single large area p-n junction.

2. The method according to claim 1, further comprising the step of forming a diaphragm on said first substrate.

3. The method according to claim 1, further comprising the step of forming said porous region and said layer in a mesa-like configuration.

4. The method according to claim 3, further comprising the step of forming a diaphragm on said first substrate.

5. The method according to claim 3, further comprising the steps of:

providing a second substrate of said semiconducting material having a conductivity opposite to said given conductivity;

forming a plurality of interspaces in said second substrate;

bonding said second substrate to a surface of said first substrate having said mesa-like configuration to provide a stress concentrator for said device; and

forming electrical contacts on said first substrate and on said second substrate.

6. The method according to claim 1, wherein said semiconducting material is silicon.

7. The method according to claim 2, wherein said semiconducting material is silicon carbide.

8. A method of fabricating a stress sensitive semiconductor device comprising the steps of:

providing a first substrate of a semiconductor material having a given conductivity;

forming a porous region on said first substrate, said porous region being of said given conductivity; and

growing a layer of said semiconducting material on said porous region, forming said porous region and said layer in a mesa-like configuration, said layer being of a conductivity opposite to said given conductivity thereby forming an array of p-n junctions between said porous region and said layer, said p-n junctions being coupled together by said layer as a single large area p-n junction;

forming a diaphragm on said first substrate;

providing a second substrate of said semiconducting material having a conductivity opposite to said given conductivity;

forming plurality of interspaces in said second substrate;

bonding said second substrate to said first substrate to providing a stress concentrator to said device; and

forming electrical contacts on said first substrate and on said second substrate.

9. The method according to claim 8, wherein said semiconducting material is silicon.

10. The method according to claim 8, wherein said semiconducting material is silicon carbide.