Method of producing VDMOS device of increased power density

• US 5,405,794 A
• Filed: 06/14/1994
• Issued: 04/11/1995
• Est. Priority Date: 06/14/1994
• Status: Expired due to Fees

• Current Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Kim, Manjin J.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Mason, David
• Application Number:
  US08/259,769
• Time in Patent Office: 301 Days
• Field of Search: 437/41, 437/67, 437/203, 437/913, 148/DIG. 126, 257/330-334
• US Class Current: 438/270
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A vertical double diffused metal-on-semiconductor device is produced by a method involving the formation of horizontally separated bodies of heavily doped Si and sources by a self-aligned process and a lift-off process along with the formation of trenches having negatively-sloped side-walls.

Claims

1. A method of producing a vertical DMOS device comprising the steps:

a) providing on an n++doped semiconductor substrate a first epitaxy n-doped Si layer and providing in the surface of said first n-doped Si layer a first p-doped Si layer,

b) forming a first thin Si oxide layer on said first p-doped Si layer,

c) forming a first photoresist pattern wherein portions of the surface of said first thin Si oxide layer are exposed in negatively sloped trenches of said first photoresist pattern,

d) forming, in said trenches source regions of horizontally separated bodies of n+doped Si in the surface of said p-doped Si layer covered only by said first Si oxide layer,

e) depositing a first layer of a conductive metal of a thickness so as to cover the exposed portions of said first thin Si oxide layer and essentially all of the sidewall surfaces of said first photoresist pattern while leaving exposed only the areas of the upper edges of the sidewall surfaces of said trenches,

f) removing said first photoresist pattern and metal deposited thereon thereby leaving remaining on said first Si oxide layer, horizontally separated metal portions, over said bodies of n+doped Si, each body having on a surface said layer of said metal portions contacting the surface of a portion of said first Si oxide layer contacting only the surface of said horizontally separated bodies of n+ doped Si,

g) providing areas of p+doped Si between said bodies of n+doped Si,

h) removing said remaining portions of said first layer of conductive metal,

i) depositing a thin layer of nitride on said first thin Si oxide layer and a first thick layer of low temperature oxide, LTO, on said nitride layer,

j) forming a second photoresist pattern on said first layer of LTO so as to expose only areas of said first layer of LTO provided above the center areas of said bodies of n+doped Si,

k) removing by plasma etching exposed portions of said first layer of LTO and all portions of underlying layers extending to said first epitaxy n-doped Si layer so as to form first trenches between said source regions of n+doped Si thereby exposing portions of said first epitaxy n-doped Si layer in said trenches,

l) removing said second photoresist pattern,

m) oxidizing the inner surfaces of said first trenches,

n) depositing n+doped poly Si in said first trenches and on the surface of said thick layer of LTO, so as to fill up said first trenches,

o) removing essentially all of said n+doped poly Si extending above said thick layer of LTO thereby forming horizontally aligned n+doped poly Si gates,

p) removing remaining portions of said first thick layer of LTO,

q) oxidizing the portions of said n+doped poly Si extending above said nitride layer to thereby cap said poly Si gates,

r) depositing a second thick LTO layer on said capped poly Si gates and said nitride layer,

s) removing by anisotropic plasma etching, said second LTO layer from said nitride layer and from said capped poly gates except from the sidewall surfaces of said capped bodies extending above said nitride layer,

t) removing, by wet isotropic etching, said nitride layer and said first Si oxide layer underneath said nitride layer thereby exposing surfaces of Si extending between said capped poly gates,

u) depositing a layer of conductive metal on the surface of the resultant structure to form source contacts.

3. The method of claim 1, wherein the first p-doped Si layer is provided in the first n-doped Si layer by boron implantation.

4. The method of claim 3, wherein the plasma etching carried out in step "k" is reactive ion etching.

5. The method of claim 4, wherein the plasma etching carried out in step "s" is reactive ion etching.

6. The method of claim 1, wherein the bodies of n+doped Si are formed by implantation and drive in of an n-type dopant selected from the group consisting of As, P and Sb in the surface of the portions of the p-doped Si layer present in the trenches formed by the first photoresist pattern.

7. The method of claim 6 wherein the concentration of dopant in the bodies of n+doped Si is 10²⁰ -3×

10²⁰ cm^-3.

8. The method of claim 6 wherein the source regions of p+doped Si is doped to a dopant concentration greater than 10¹⁹ cm^-3 by implantation and drive in of boron.

2. A method of producing a vertical DMOS semiconductor device said method comprising the steps:

a) providing on a semiconductor substrate very heavily doped with a dopant of a first conductivity type a first epitaxial, epi, Si layer lightly doped with a dopant of said first conductivity type and providing in said first Si layer a second Si layer moderately doped with a dopant of a second, electrically opposing, conductivity type,

b) forming a first, thin, Si oxide layer on said second Si layer,

c) forming a photoresist pattern having negatively sloped first trenches in which portions of the surface of said first Si oxide layer are exposed,

d) forming, in said first photoresist trenches source regions of separated horizontally separated first bodies of Si heavily doped with a dopant of said first conductivity type in the surface of said second, moderately doped Si layer covered only by said first Si oxide layer,

e) depositing a first layer of a conductive metal of a thickness so as to cover the exposed portions of said first Si oxide layer and essentially all of the sidewall surfaces of said first photoresist pattern while leaving exposed only the upper areas of the upper edges of the sidewall surfaces of said first trenches,

f) removing said first photoresist pattern and metal deposited thereon thereby leaving remaining on said first Si oxide layer horizontally separated metal bodies, each of said metal bodies contacting a surface of a portion of said first Si oxide layer contacting only the surface of one of said horizontally separated first bodies of Si heavily doped with a dopant of the first conductivity type,

g) providing second bodies of Si heavily doped with a dopant of said second conductivity type between said source regions of said first horizontally separate bodies of Si heavily doped with a dopant of said first conductivity type,

h) removing said metal bodies,

i) depositing a thin layer of a metal nitride on said first Si oxide layer,

j) depositing a first thick layer of low temperture oxide, LTO, on said metal nitride layer,

k) forming a second photoresist pattern on said first layer of LTO so as to expose only areas of said first thick layer of LTO provided above said horizontally separated first bodies of Si,

l) removing, by plasma etching, said exposed areas of said first thick layer of LTO and all portions of layers underlying said exposed areas extending to said first epi Si layer so as to form second trenches between said source regions of said first bodies of heavily doped Si thereby exposing portions of said first epi lightly doped Si layer within said trenches,

m) removing said second photoresist pattern,

n) oxidizing the inner surfaces of the walls of said second trenches,

o) depositing poly Si heavily doped with a dopant of said first conductivity type in said second trenches, so as to fill up said second trenches, and on said first thick layer of LTO,

p) removing essentially all of said poly Si extending above said first layer of LTO thereby forming horizontally aligned poly Si gates,

q) removing remaining portions of said first layer of LTO by anisotropic ion etching,

r) oxidizing the portions of said poly Si extending above said nitride layer to thereby cap said poly Si gates,

s) depositing a second thick LTO layer on said capped poly Si gates and on said nitride layer,

t) removing, by anisotropic plasma etching, said second thick LTO layer from said nitride layer and from said capped poly Si gates except for the surfaces of said capped Si gates extending above said nitride layer, thereby providing oxide spacers extending from the edges of the Si gates to the nitride layer,

u) removing, by wet isotropic etching, said nitride layer and said first Si oxide layer underneath said nitride layer thereby exposing surfaces of Si extending between said capped poly Si gates,

v) depositing a layer of conductive metal on the surface of said resultant structure to form source contacts.