Method of forming a SOI transistor having a self-aligned body contact

• US 5,405,795 A
• Filed: 06/29/1994
• Issued: 04/11/1995
• Est. Priority Date: 06/29/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Buti, Taqi N., Beyer, Klaus D., Hsieh, Chang-Ming
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US08/268,380
• Time in Patent Office: 286 Days
• Field of Search: 437/40, 437/41, 437/43, 437/62, 437/89, 437/90, 437/228, 437/913, 437/915, 148/Dig. 150
• US Class Current: 438/151
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

Claims

1. A method of forming a SOI field effect transistor comprising a source and drain doped with a first polarity and formed in a silicon layer doped with a second polarity and disposed above an insulating substrate and a gate insulator and gate disposed above a body portion of said silicon layer between said source and drain, and having a gate extension connected to said gate and also disposed above said gate insulator and above a collection portion of said silicon layer, said body portion and said collection portion being in proximity;

and

a collection electrode doped with said second polarity and disposed in said silicon layer on a collection side of said gate extension, whereby minority carriers may flow from said body through said collection portion of said silicon layer to said collection electrode, comprising the steps of;

defining an active transistor area in said silicon layer;

forming a gate stack comprising a gate oxide, gate and gate dielectric having a gate dielectric top surface;

patterning said gate stack to define said gate and said gate extension and further defining source and drain areas adjacent said gate in said active area, whereby said gate has a gate length between said source and drain;

forming insulating gate sidewalls on edges of said gate adjacent said source and drain;

forming raised conductive source and drain members above said source and drain and isolated from said gate by said insulating gate sidewalls;

forming cap dielectric members above said raised source and drain members, said cap dielectric having a cap top surface higher than said gate dielectric top surface and having sidewall-defining edges adjacent said gate extension;

depositing a first conformal layer of an aperture-defining dielectric above said gate dielectric and cap dielectric, thereby defining an aperture location above said gate dielectric having a bottom covered with said first conformal dielectric and interior aperture sidewalls above said sidewall-defining edges of said cap dielectric;

etching directionally through said aperture-defining dielectric and said gate extension to form a collection electrode aperture, thereby forming a sidewall support member from that portion of said gate extension below said interior aperture sidewalls;

depositing a conformal sidewall layer of dielectric extending into said collection electrode aperture; and

directionally etching said conformal sidewall layer of dielectric, thereby forming insulating interior sidewalls on interior walls of said collection aperture, said interior walls including a portion of said gate extension disposed between said collection aperture and said source and drain.

2. A method according to claim 1, in which said gate dielectric is formed from a layer of nitride, said raised source and drain members are formed from poly, and said step of forming cap dielectric members comprises growing a layer of thermal oxide above said poly raised source and drain members, whereby said cap dielectric members are self-aligned above said source and drain.

3. A method according to claim 1, in which said step of forming insulating gate sidewalls is followed by a step of implanting source and drain dopants.

4. A method according to claim 3, in which said step of etching directionally through said aperture-defining dielectric and said gate extension is followed by a step of oxidizing exposed portions of said gate.

5. A method according to claim 1, in which said step of depositing said aperture-defining dielectric includes depositing a layer having a thickness greater than about half of said gate length, whereby said layer of aperture-defining dielectric protects said gate during said step of etching directionally through said layer of aperture-defining dielectric.

6. A method according to claim 5, in which said gate dielectric is formed from a layer of nitride, said raised source and drain members are formed from poly, and said step of forming cap dielectric members comprises growing a layer of thermal oxide above said poly raised source and drain members, whereby said cap dielectric members are self-aligned above said source and drain.

7. A method according to claim 6, in which said step of forming insulating gate sidewalls is followed by a step of implanting source and drain dopants.

8. A method according to claim 7, in which said gate dielectric is formed from a layer of nitride, said raised source and drain members are formed from poly, and said step of forming cap dielectric members comprises growing a layer of thermal oxide above said poly raised source and drain members, whereby said cap dielectric members are self-aligned above said source and drain.

9. A method according to claim 8, in which said step of forming insulating gate sidewalls is followed by a step of implanting source and drain dopants.

10. A method according to claim 1, further including a step of protecting said gate with a non-critical blockout mask during said step of etching directionally through said aperture-defining dielectric.