Interconnection construction of semiconductor device

• US 5,406,108 A
• Filed: 09/20/1993
• Issued: 04/11/1995
• Est. Priority Date: 11/17/1992
• Status: Expired due to Fees

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Inada, Hiroshi
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): BOWERS, COURTNEY
• Application Number:
  US08/123,267
• Time in Patent Office: 568 Days
• Field of Search: 257/415, 257/417, 257/53, 257/418, 257/690, 257/698, 257/730, 257/773, 257/786
• US Class Current: 257/415
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 2015/0828 the mass being of the paddle type being suspended at one of its longitudinal ends

Abstract

A semiconductor device such as a semiconductor acceleration sensor of an electrostatic capacity type and a method of manufacturing the same are disclosed, wherein a silicon layer is bonded to first and second glass layers by means of an anodic bonding process in such a manner as to be positioned between the first and second glass layers. The first glass layer has an overhung portion protruded from an edge of the second glass layer. At least an interconnection is formed between the silicon layer and the first glass layer and has a bonding pad positioned on the inner surface of the overhung portion of the first glass layer. Before the anodic bonding process, an anodic-bonding-inhibition-layer such as aluminum layer is positioned between a second glass wafer forming the second glass layer and a silicon wafer forming the silicon layer, and faces to a predetermined portion of a first glass wafer forming the first glass layer. The predetermined portion of the first glass wafer is to be the overhung portion of the first glass layer. During a dicing process after the anodic bonding process, the second glass wafer is cut along the configuration of the anodic-bonding-inhibition-layer, thereby removing an unnecessary portion of the second glass wafer facing to the overhung portion of the first glass layer from the remaining portions of the second glass wafer.

Claims

1. A semiconductor device comprising:

first and second glass layers spaced apart from and parallel to each other, said first glass layer having a main portion facing said second glass layer and an overhanging portion protruding beyond an edge of said second glass layer;

a silicon layer bonded to said first and second glass layers in such a manner as to be positioned between said first and second glass layers; and

first and second interconnections spaced apart from each other and formed between said silicon layer and said first glass layer, said first and second interconnections respectively having bonding pads positioned on an inner surface of said overhanging portion of said first glass layer,

wherein said silicon layer has an overhanging portion which protrudes beyond said second glass layer so as to be positioned between the bonding pads of said first and second interconnections.

3. A semiconductor device as set forth in claim 1, further comprising a static electrode formed on an inner surface of the main portion of said first glass layer and electrically connected to said first interconnection,

wherein said silicon layer includes a cantilever portion having a free end portion which is electrically connected to said second interconnection, said free end portion facing said static electrode to serve as a movable electrode, and electrostatic capacity between said static electrode and said movable electrode being varied in response to displacement of said free end portion of said cantilever portion with respect to said static electrode.

2. A semiconductor device comprising:

first and second glass layers spaced apart from and parallel to each other, said first glass layer having a main portion facing said second glass layer and an overhanging portion protruding beyond an edge of said second glass layer;

a silicon layer bonded to said first and second glass layers in such a manner as to be positioned between said first and second glass layers;

a first interconnection formed between said silicon layer and said first glass layer and having a bonding pad positioned on an inner surface of said overhanging portion of said first glass layer;

a second interconnection formed between said silicon layer and said second glass layer; and

a third interconnection formed between said silicon layer and said first glass layer and spaced apart from said first interconnection, said third interconnection having a bonding pad positioned on the inner surface of said overhanging portion of said first glass layer,

wherein said silicon layer has a conductive isolated portion insulated from the rest of said silicon layer, said first interconnection being electrically connected to said second interconnection through said conductive isolated portion, and

wherein said silicon layer has an overhanging portion which protrudes beyond said second glass layer so as to be positioned between the bonding pads of said first and third interconnections.