Amplifier system for low level sensor signal

• US 5,406,223 A
• Filed: 11/20/1992
• Issued: 04/11/1995
• Est. Priority Date: 11/20/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Vulih, Salomon, Wittlinger, Harold A., Olmstead, John A.
• Primary Examiner(s): Mullins, James B.
• Assistant Examiner(s): DUDEK, JAMES A
• Application Number:
  US07/979,209
• Time in Patent Office: 872 Days
• Field of Search: 330/258, 330/252, 330/261, 330/296, 330/310, 330/147, 330/295, 330/124 R, 73/861.44, 73/861.22, 73/861.25, 73/861.26, 324/123 R, 324/123 C, 324/124
• US Class Current: 330/258
• CPC Class Codes: H03F 2203/45658 the LC comprising two diodes of current mirrors
• CPC Class Codes: H03F 2203/45711 the LC comprising two anti-phase controlled SEPP circuits as output stages, e.g. fully differential
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45645 Controlling the input circuit of the differential amplifier
• CPC Class Codes: H03F 3/4565 Controlling the common source circuit of the differential amplifier

Abstract

An amplifier system embodying the invention includes an input stage comprising one or more differential amplifiers having a high degree of common mode rejection. The inputs of the differential amplifiers of the input stage are AC coupled to different signal input terminals which are adapted to receive small information signals riding on large common mode signals. The AC coupling blocks any dc level associated with the input signals from affecting the amplifier system and the high degree of common mode rejection maintains the gain of the amplifiers relatively constant over a wide range of common mode signals. The outputs of the differential amplifiers of the input stage are connected in common to an output node to sum their output signals and to reduce random noise associated with the input signals and the input stage. The output node of the input stage is AC coupled to the input of a second stage whose output is in turn AC coupled to a third output stage to reduce the effect of amplifier offsets. The gain of the amplifier system is controlled by low pass filters connected to the output node of the input stage and to the output of the second stage. In certain embodiments a biasing clock is coupled via resistors to the inputs of the differential amplifiers to generate a dc bias level at their inputs which is a function of the duty cycle of the clock, the resistor connected at the input and coupling capacitor connected to the input.

Claims

1. A combination comprising:

first and second transconductance differential amplifiers, each transconductance differential amplifier (TDA) having first and second input terminals and an output terminal, and each TDA being characterized as having a high output impedance and producing a signal output current which is proportional to a voltage differential signal across its inputs;

means for capacitively coupling a first pair of input signals to the first and second input terminals of the first TDA;

means for capacitively coupling a second pair of input signals to the first and second input terminals of the second TDA;

means for biasing each differential input terminal of each TDA to a selective level; and

means direct current connecting the outputs of the first and second TDAs via negligible impedance means to a common output terminal for summing their signal output currents.

2. A combination as claimed in claim 1, wherein said means for capacitively coupling includes a first capacitor connected between a first signal source and the first input terminal of the first TDA, a second capacitor connected between a second signal source and the second input of the first TDA, a third capacitor connected between a third signal source and the first input terminal of the second TDA and a fourth capacitor connected between a fourth signal source and the second input terminal of the second TDA.

3. The combination as claimed in claim 2, wherein said first, second, third and fourth signal sources are sensors, each sensor producing an information signal and a common mode signal whose amplitude is much larger than the amplitude of the information signal.

4. The combination as claimed in claim 3, wherein said means for biasing each differential input terminal of each TDA includes:

a biasing terminal adapted to receive a clocking signal;

a first impedance means connected between said first differential input terminal of each differential amplifier and said biasing terminal; and

a second impedance means connected between said second differential input terminal of each differential amplifier and said biasing terminal.

5. The combination comprising:

N pairs of input terminals;

where N is an integer equal to or greater than one;

means for applying a pair of input signals to each pair of said N pairs of input terminals;

each pair of signals including a common mode signal applied to each input terminal of a pair and a differential signal applied between the two terminals of a pair;

N transconductance differential amplifiers, one per pair of input terminals;

each differential amplifier having first and second differential input terminals and an output terminal and including means for providing a high degree of common mode rejection;

alternating current (AC) means coupling each pair of input terminals to the differential input terminals of each differential amplifier;

direct current means connecting the outputs of the N differential amplifiers in common to a common output terminal; and

means for biasing the differential input terminals of each differential amplifier to a voltage level comprising;

a biasing terminal adapted to receive a clocking signal;

a first impedance means connected between said first differential input terminal of each differential amplifier and said biasing terminal; and

a second impedance means connected between said second differential input terminal of each differential amplifier and said biasing terminal.

6. The combination as claimed in claim 5, further including an additional amplifier in addition to said N amplifiers, said additional amplifier having an input and an output;

and

means AC coupling the input of said additional amplifier to said common output terminal.

7. The combination as claimed in claim 6, further including means for biasing the input of said additional amplifier to a desired voltage level comprising an additional impedance means connected between said biasing terminal and the input of said additional amplifier.

8. The combination as claimed in claim 7, further including a comparator amplifier having an input and an output;

and means AC coupling the input of said comparator amplifier to said output of said additional amplifier.

9. The combination as claimed in claim 8, further including means for biasing the input of said comparator amplifier stage to a desired voltage level comprising a still further impedance means connected between said biasing terminal and the input of said comparator amplifier.

10. The combination as claimed in claim 6, further including a first low pass filter connected to said common output terminal for controlling the gain of said N transconductance amplifiers and further including a second low pass filter connected to the output of said additional amplifier for controlling its gain.

11. The combination as claimed in claim 5, wherein N is equal to two.

12. The combination as claimed in claim 5, wherein each signal of the pair of signals includes a common mode signal on which there rides an information signal.

13. An amplifier system for amplifying input signals having an information signal component riding on a large common mode signal component comprising:

input means adapted to receive said input signals;

a first differential amplifier (diff-amp) means having first and second differential inputs and an output and characterized in having a high degree of common mode rejection;

coupling capacitors connected between said input means and each differential input of said first diff-amp means for AC coupling the input signals to the differential inputs of the first diff-amp means;

a second amplifier and an output amplifier, each amplifier having an input and an output;

another coupling capacitor connected between the output of said first diff-amp means and the input of said second amplifier, and still another coupling capacitor connected between the output of said second amplifier and,the input of said output amplifier; and

means for generating a bias level at the inputs of said first diff-amp means comprising a bias terminal for the application thereto of a biasing clock signal and an impedance means connected between each diff-amp input and said bias terminal for producing a bias level at each diff-amp input which is a function of the duty cycle of the clock and its associated impedance means and coupling capacitor.

14. The combination as claimed in claim 13 wherein said first differential amplifier means includes:

(a) first and second differential amplifiers, each differential amplifier having first and second differential inputs and an output;

(b) means AC coupling the differential inputs of each amplifier to said input means; and

(c) means connecting the outputs of said first and second differential amplifiers in common to said output of said differential amplifier means.

15. The combination as claimed in claim 13 wherein said impedance means are resistors.