Methods and apparatus for the quantization and analog conversion of digital signals
First Claim
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1. A dual DAC, comprising:
- a ROM containing a plurality of addressable output signals;
a shift left register configured to receive one of said output signals from said ROM at time t0 ;
a shift right register configured to receive said one of said output signals from said ROM at time t0 ;
a first one bit DAC configured to receive a left shifted output from said shift left register at time t1 following time t0 ;
a second one bit DAC configured to receive a right shifted output from said shift right register at time t1 ; and
an analog summer configured to receive the respective outputs of said first and second one bit DACs at time t2 following time t1, said summer being further configured to generate an output signal indicative of the sum of the outputs from said first and second one bit DACs.
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Abstract
A digital-to-analog converter (DAC) for generating a pulse width modulated (PWM) signal. A dual-DAC implementation includes a read-only memory (ROM) containing a plurality of addressable output signals, respective shift left and shift right registers configured to simultaneously receive an output signal from the ROM, and respective first and second DACs are configured to receive the left shifted output and right shifted output, respectively, from the shift left and shift right registers. Both DAC outputs are applied to an analog summer which generates an output signal indicative of the sum of the outputs from the two DACs.
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Citations
14 Claims
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1. A dual DAC, comprising:
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a ROM containing a plurality of addressable output signals; a shift left register configured to receive one of said output signals from said ROM at time t0 ; a shift right register configured to receive said one of said output signals from said ROM at time t0 ; a first one bit DAC configured to receive a left shifted output from said shift left register at time t1 following time t0 ; a second one bit DAC configured to receive a right shifted output from said shift right register at time t1 ; and an analog summer configured to receive the respective outputs of said first and second one bit DACs at time t2 following time t1, said summer being further configured to generate an output signal indicative of the sum of the outputs from said first and second one bit DACs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification