Multi-lane controller
First Claim
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1. A multi-lane controller comprising:
- a first lane;
a second lane; and
a lane selector;
said first lane comprising a first control data processor, a first data flow controller, a first signal path, a first input/output interface connected to said first data flow controller by said first signal path, a first lane input, and a first lane output, said first control data processor being connected via said first data flow controller, said first signal path, and said first input/output interface to said first lane input and said first lane output;
said second lane comprising a second control data processor, a second data flow controller, a second signal path, a second input/output interface connected to said second data flow controller by said second signal path, a second lane input, and a second lane output, said second control data processor being connected via said second data flow controller, said second signal path, and said second input/output interface to said second lane input and said second lane output;
said first data flow controller having first and second inputs connected to said first and second signal paths, respectively, to receive input data from said first and second input/output interfaces, respectively, and to supply the input data to said first control data processor, said second data flow controller having third and fourth inputs connected to said first and second signal paths, respectively, to receive the input data from said first and second input/output interfaces, respectively, and to supply the input data to said second control data processor, said first and second data flow controllers being arranged to supply output data from said first and second control data processors to said first and second input/output interfaces, respectively;
said data flow controller of each one of said lanes comprising first to fourth read/write memories having respective write inputs and read outputs, said first read/write memory having a write input connected to said control data processor of said one lane and a read output connected to said interface of said one lane, said second read/write memory having a write input connected to said control data processor of said one lane and a read output connected to said interface of an other of said lanes, said third read/write memory having a write input connected to said interface of said one lane and a read output connected to said control data processor of said one lane, and said fourth read/write memory having a write input connected to said interface of said other lane and a read output connected to said control data processor of said one lane; and
said lane selector being arranged to permit the supply of output data to said lane output of one of said first and second lanes and to inhibit the supply of output data to said lane output of another of said first and second lanes.
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Abstract
A multi-lane controller providing redundancy comprises two lanes. Each lane comprises an input/output interface, a data flow controller and a control data processor. Each data flow controller receives input data from and supplies output data to both input/output interfaces. The information exchange between each lane does not rely on the proper operation of either the control data processor or data flow controller of any of the lanes.
19 Citations
9 Claims
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1. A multi-lane controller comprising:
a first lane;
a second lane; and
a lane selector;
said first lane comprising a first control data processor, a first data flow controller, a first signal path, a first input/output interface connected to said first data flow controller by said first signal path, a first lane input, and a first lane output, said first control data processor being connected via said first data flow controller, said first signal path, and said first input/output interface to said first lane input and said first lane output;
said second lane comprising a second control data processor, a second data flow controller, a second signal path, a second input/output interface connected to said second data flow controller by said second signal path, a second lane input, and a second lane output, said second control data processor being connected via said second data flow controller, said second signal path, and said second input/output interface to said second lane input and said second lane output;
said first data flow controller having first and second inputs connected to said first and second signal paths, respectively, to receive input data from said first and second input/output interfaces, respectively, and to supply the input data to said first control data processor, said second data flow controller having third and fourth inputs connected to said first and second signal paths, respectively, to receive the input data from said first and second input/output interfaces, respectively, and to supply the input data to said second control data processor, said first and second data flow controllers being arranged to supply output data from said first and second control data processors to said first and second input/output interfaces, respectively;
said data flow controller of each one of said lanes comprising first to fourth read/write memories having respective write inputs and read outputs, said first read/write memory having a write input connected to said control data processor of said one lane and a read output connected to said interface of said one lane, said second read/write memory having a write input connected to said control data processor of said one lane and a read output connected to said interface of an other of said lanes, said third read/write memory having a write input connected to said interface of said one lane and a read output connected to said control data processor of said one lane, and said fourth read/write memory having a write input connected to said interface of said other lane and a read output connected to said control data processor of said one lane; and
said lane selector being arranged to permit the supply of output data to said lane output of one of said first and second lanes and to inhibit the supply of output data to said lane output of another of said first and second lanes.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
Specification
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Current AssigneeLucas Industries Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
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Original AssigneeLucas Industries Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
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InventorsTipton, James, Simmons, John R., Smout, Peter D.
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Primary Examiner(s)Envall, Jr., Roy N.
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Assistant Examiner(s)TOUSI, CAMERON
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Application NumberUS07/985,031Time in Patent Office859 DaysField of Search364/133, 364/431.01, 364/431.04, 364/944.61, 364/184, 364/187, 364/268-268.8, 370/85.11, 370/14, 370/16, 395/325US Class Current700/4CPC Class CodesG05B 9/03 with multiple-channel loop,...
