Mechanism for preventing radiation induced latch-up in CMOS integrated circuits
First Claim
1. A CMOS circuit formed in a semiconductor substrate having a circuit-bearing-surface with a p-type region and an n-type region, the circuit includes a Vdd power supply and a Vss power supply, the circuit having improved immunity to radiation induced latch-up and comprising:
- a. an n-channel transistor formed in the p-type region of the substrate having a source coupled to Vss;
b. a p-channel transistor formed in the n-type region of the substrate having a drain coupled to the n-channel transistor and a source coupled to Vdd;
c. a single p+guard formed between the n-channel transistor and the n-type region wherein the p+guard is electrically coupled to Vss; and
d. a single n+guard formed between the p-channel transistor and the p-type region wherein the n+guard is electrically coupled to Vdd,the circuit further comprising means for improving immunity to a single event upset comprising;
e. an n-channel network of devices for performing a function, the n-channel network having a plurality of n-channel control devices and a plurality of n-channel load devices;
f. a p-channel network of devices for performing the function, the p-channel network having a plurality of p-channel control devices and a plurality of p-channel load devices; and
g. means for cross coupling the n-channel network and the p-channel network such that an n-channel control device controls a p-channel load device and a p-channel control device controls an n-channel load device.
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Abstract
A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present invention can be utilized with N-Well, P-Well and dual Well processes. For example, the circuit is described relative to an N-Well process. An N-Well is formed in a p-type substrate. A network of p-channel transistors are formed in the N-Well and a network of n-channel transistors are formed in the p-type substrate. A continuous P+guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and the N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between the p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a parasitic SCR and also act as additional collectors of radiation induced current. Single event upset immunity is improved by forming duplicate functions in an n-channel network and a p-channel network. N-channel control transistors are coupled to control p-channel load transistors and p-channel control transistors are coupled to control n-channel load transistors.
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Citations
13 Claims
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1. A CMOS circuit formed in a semiconductor substrate having a circuit-bearing-surface with a p-type region and an n-type region, the circuit includes a Vdd power supply and a Vss power supply, the circuit having improved immunity to radiation induced latch-up and comprising:
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a. an n-channel transistor formed in the p-type region of the substrate having a source coupled to Vss; b. a p-channel transistor formed in the n-type region of the substrate having a drain coupled to the n-channel transistor and a source coupled to Vdd; c. a single p+guard formed between the n-channel transistor and the n-type region wherein the p+guard is electrically coupled to Vss; and d. a single n+guard formed between the p-channel transistor and the p-type region wherein the n+guard is electrically coupled to Vdd, the circuit further comprising means for improving immunity to a single event upset comprising; e. an n-channel network of devices for performing a function, the n-channel network having a plurality of n-channel control devices and a plurality of n-channel load devices; f. a p-channel network of devices for performing the function, the p-channel network having a plurality of p-channel control devices and a plurality of p-channel load devices; and g. means for cross coupling the n-channel network and the p-channel network such that an n-channel control device controls a p-channel load device and a p-channel control device controls an n-channel load device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A CMOS circuit formed in a semiconductor substrate having a first-doping-type, the circuit including a first and a second power supply, the circuit having improved immunity to radiation induced latch-up and comprising:
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a. a well formed in the substrate of a second-doping-type, wherein the second-doping-type is opposite polarity of the first-doping-type; b. a plurality of first-doping-type-channel transistors formed in the second-doping-type well each having an electrode electrically coupled to the first power supply; c. a plurality of second-doping-type-channel transistors formed in the substrate outside of the well each having an electrode electrically coupled to the second power supply; d. a single second-doping-type guard formed between the first-doping-type-channel transistors and the substrate, wherein the second-doping-type guard is electrically coupled to the first power supply; and e. a single first-doping-type guard formed between the second-doping-type-channel transistor and the well, wherein the first-doping type guard is electrically coupled to the second power supply, the circuit further comprising means for improving immunity to a single event upset comprising; f. a first-doping-type-channel network of devices for performing a function, the first-doping-type-channel network having a plurality of first-doping-type-channel control devices and a plurality of first-doping-type-channel load devices; g. a second-doping-type-channel network of devices for performing the function, the second-doping-type-channel network having a plurality of second-doping-type-channel control devices and a plurality of second-doping-type-channel load devices; and h. means for cross coupling the first-doping-type-channel network and the second-doping-type-channel network such that an first-doping-type-channel control device controls a second-doping-type-channel load device and a second-doping-type-channel control device controls and first-doping-type-channel load device. - View Dependent Claims (10, 11, 12, 13)
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Specification