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Mechanism for preventing radiation induced latch-up in CMOS integrated circuits

  • US 5,406,513 A
  • Filed: 02/05/1993
  • Issued: 04/11/1995
  • Est. Priority Date: 02/05/1993
  • Status: Expired due to Term
First Claim
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1. A CMOS circuit formed in a semiconductor substrate having a circuit-bearing-surface with a p-type region and an n-type region, the circuit includes a Vdd power supply and a Vss power supply, the circuit having improved immunity to radiation induced latch-up and comprising:

  • a. an n-channel transistor formed in the p-type region of the substrate having a source coupled to Vss;

    b. a p-channel transistor formed in the n-type region of the substrate having a drain coupled to the n-channel transistor and a source coupled to Vdd;

    c. a single p+guard formed between the n-channel transistor and the n-type region wherein the p+guard is electrically coupled to Vss; and

    d. a single n+guard formed between the p-channel transistor and the p-type region wherein the n+guard is electrically coupled to Vdd,the circuit further comprising means for improving immunity to a single event upset comprising;

    e. an n-channel network of devices for performing a function, the n-channel network having a plurality of n-channel control devices and a plurality of n-channel load devices;

    f. a p-channel network of devices for performing the function, the p-channel network having a plurality of p-channel control devices and a plurality of p-channel load devices; and

    g. means for cross coupling the n-channel network and the p-channel network such that an n-channel control device controls a p-channel load device and a p-channel control device controls an n-channel load device.

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