Flash non-volatile memory

• US 5,406,529 A
• Filed: 09/21/1993
• Issued: 04/11/1995
• Est. Priority Date: 09/22/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Asano, Hideo
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/125,058
• Time in Patent Office: 567 Days
• Field of Search: 365/900, 365/218, 365/200, 365/201, 395/425, 395/400
• US Class Current: 365/230.03
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A flash-erase memory includes a plurality of blocks accessible by a processor and, in association with each block, a block ID representing an address (RBA) specified by the processor upon writing, a revision code (RC) indicating how many times the processor performed writing using the same RBA, and an erase count (EC) indicating the number of times of erasing of this block are stored. Writing is performed to a writable block having the minimum erase count, and if there is a different block having the same block ID as the address specified by the processor, its revision code is updated and used as a revision code of the written block, and the different block is erased and its erase count is updated.

Claims

1. A flash non-volatile memory, comprising:

a plurality of non-volatile memory blocks accessible by a processor;

means for maintaining control information in each block, said control information including a respective block ID representing a relative block address specified by said processor upon writing, and an erase count indicating the number of times each respective block has been erased;

means, responsive to a request to write data to said flash non-volatile memory at a specified relative block address, for identifying a writable block having a minimum erase count;

means for writing said data to said identified block having a minimum erase count; and

means for updating said block ID contained in said control information to correspond to said specified relative block address.

2. The flash non-volatile memory according to claim 1, wherein:

said control information further includes a revision code for each block, said revision code having a value indicating how many times said processor performed writing to the block D of the respective block; and

said memory further comprises;

means for replacing a revision code value associated with said identified block having a minimum erase count with a revision code value obtained by updating a revision code value of a second block having the same block ID as said block ID represented by said specified address;

means for erasing said second block; and

means, responsive to said means for erasing, for updating the erase count in said control information associated with said second block.

3. The flash non-volatile memory according to claim 2, wherein the revision code of said identified block is set to a first value if said second block does not exist.

4. The flash non-volatile memory according to claim 2, wherein said revision code and said erase count are updated by incrementing by one.

5. The flash non-volatile memory according to claim 1, wherein each of said plurality of blocks comprises a header section and a data section, and said control information is stored in said header section.

6. The flash non-volatile memory according to claim 5, wherein when a block is erased, an erase count included in its header section is updated and written back to said header section of said block.

7. A solid state file apparatus which is accessed by a relative block address from a processor, comprising:

a controller for connecting to said processor; and

a flash non-volatile memory connected to said controller and including a plurality of blocks accessible by said processor, each block of said flash non-volatile memory comprising a header section and a data section, said header section including a block ID representing a relative block address specified by said processor upon writing to the respective block, and an erase count indicating the number of times the respective block has been erased;

wherein said controller further comprises;

(a) means, responsive to a request by said processor to write data to a specified relative block address, for identifying a writable block in said flash non-volatile memory having a minimum erase count;

(b) means for writing data for said processor to the data section of said identified block having a minimum erase count; and

(c) means for writing to the header section of said identified block having a minimum erase count a block ID represented by said specified relative block address.

8. The solid state file apparatus according to claim 7, further comprising:

a random access memory connected to said controller; and

means in said controller for creating a memory management table in said random access memory having entries corresponding to the respective blocks by sequentially reading from each block of said flash non-volatile memory the contents of the header section and writing into said random access memory.

9. The solid state file apparatus according to claim 8, wherein each entry of said memory management table contains, in addition to the contents of the header section of a corresponding block, a physical address of said corresponding block and a flag indicating whether said corresponding block is writable or non-writable.

10. The solid state file apparatus according to claim 7, wherein:

said header section of each block further includes a revision code, said revision code having a value indicating how many times said processor performed writing to the block ID specified in said header section; and

said controller further comprises;

(d) means for writing to the header section of said identified block having a minimum erase count a revision code value made by updating a revision code value of a second block having the same block ID as said block ID represented by said specified relative block address;

(e) means for erasing said second block; and

(f) means, responsive to said means for erasing, for updating an erase count in the header section of said second block.

11. The solid state file apparatus according to claim 10, wherein the revision code of said identified block is set to a first value if said second block does not exist.

12. The solid state file apparatus according to claim 10, further comprising:

a random access memory connected to said controller; and

means in said controller for creating a memory management table in said random access memory having entries corresponding to the respective blocks by sequentially reading from each block of said flash non-volatile memory the contents of the header section and writing into said random access memory.

13. The solid state file apparatus according to claim 12, wherein each entry of said memory management table contains, in addition to the contents of the header section of a corresponding block, a physical address of said corresponding block and a flag indicating whether said corresponding block is writable or non-writable.

14. The solid state file apparatus according to claim 13, wherein if there are two blocks having the same block ID and different revision codes when said memory management table is created, said controller erases the block having the smaller revision code, updates its erase count, and sets a flag in a corresponding entry in said memory management table to a writable state.

15. The solid state file apparatus according to claim 14, wherein said controller accesses said memory management table in response to a command from said processor and, in case of a read command, reads said flash non-volatile memory by using a physical address in an entry containing a block ID representing the relative block address of said read command, or, in case of a write command, writes said flash non-volatile memory by using a physical address in an entry in which said flag is set to the writable state and the erase count is minimum.

16. The solid state file apparatus according to claim 15, wherein upon creating said memory management table, if the revision code in the header section of one of the respective blocks read has been reset due to erasure, said controller sets the flag in a corresponding entry to the writable state, otherwise it sets to the non-writable state.