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Tamperproof arrangement for an integrated circuit device

  • US 5,406,630 A
  • Filed: 01/10/1994
  • Issued: 04/11/1995
  • Est. Priority Date: 05/04/1992
  • Status: Expired due to Fees
First Claim
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1. A tamperproof method for an integrated circuit die comprising the steps of:

  • segregating critical circuit functions from non-critical circuit functions on said integrated circuit die;

    locating said critical circuit functions substantially in the center of the integrated circuit die;

    providing temperature sensors in said critical circuit area of said integrated circuit die to detect excessive temperature;

    providing radiation sensors in said critical circuit area of said integrated circuit die to detect excessive radiation levels in said critical circuit area; and

    clearing all memory elements in said critical circuit function area, if excessive temperature or excessive radiation is detected by said temperature sensors or radiation sensors respectively.

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