Enhanced performance bipolar transistor process

• US 5,407,842 A
• Filed: 06/08/1994
• Issued: 04/18/1995
• Est. Priority Date: 03/05/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Morris, Francis J., Yang, Jau-Yuann, Yuan, Han-Tzong, Plumton, Donald L.
• Primary Examiner(s): Hearn, Brian
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US08/255,502
• Time in Patent Office: 314 Days
• Field of Search: 437/31, 437/33, 437/126, 437/133, 437/26, 437/128, 437/909, 148/DIG. 72, 148/DIG. 10
• US Class Current: 438/312
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: Y10S 148/01 Bipolar transistors-ion implantation
• CPC Class Codes: Y10S 148/072 Heterojunctions

Abstract

This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.

Claims

1. A method of forming a bipolar transistor comprising:

a. forming a subcollector layer, having a doping type and a doping level, on a substrate;

b. forming a first layer, of the same doping type and a lower doping level than said subcollector layer, over said subcollector layer;

c. increasing the doping level of first and second regions of said first layer;

d. forming a second layer, of the same doping type and a lower doping level than said subcollector layer, over said first layer;

e. increasing the doping level of a first region of said second layer which is over said first region of said first layer, whereby said subcollector layer, said first region of said first layer and said first region of said second layer are the collector of the transistor;

f. forming a base layer over said second layer of an opposite doping type than said subcollector layer; and

g. forming an emitter layer of the same doping type as said subcollector layer over said base layer.

2. The method of claim 1, wherein said subcollector layer, said first layer and said second layer are GaAs.

3. The method of claim 1, wherein said subcollector layer, said first layer and said second layer are Si.

4. The method of claim 1, wherein said base layer is carbon doped GaAs.

5. The method of claim 1, wherein said emitter layer is AlGaAs.

6. The method of claim 1, further comprising a grading layer over said emitter layer.

7. The method of claim 6, further comprising an ohmic contact layer over said grading layer.

8. The method of claim 7, wherein said ohmic contact layer is InGaAs.

9. The method of claim 1, wherein said transistor is isolated.

10. The method of claim 9, wherein said isolation is done by oxygen implants.

11. The method of claim 1, wherein base and collector contact areas are isolated.

12. The method of claim 11, wherein said isolation is done with a boron implant.

13. The method of claim 1, further comprising forming base, emitter, and collector contacts.

14. The method of claim 1, wherein said transistor is a PNP transistor.

15. The method of claim 1, wherein said transistor is an NPN transistor.

16. The method of claim 1, further comprising the step of forming an extrinsic base, of an opposite doping type than said subcollector before forming said base layer and not over said first and second regions of said first layer.

17. The method of claim 16, wherein said extrinsic base region is implanted into said second layer.

18. The method of claim 16, wherein said extrinsic base is grown over said second layer and selectively removed.

19. The method of claim 16, wherein said extrinsic base is selectively grown over said second layer.