Method of making an electrode tip for a tunnel current sensing device

• US 5,407,868 A
• Filed: 12/08/1992
• Issued: 04/18/1995
• Est. Priority Date: 12/08/1992
• Status: Expired due to Term

• Current Assignee: Alliedsignal Inc.
• Original Assignee: Alliedsignal Inc.
• Inventors: Woodruff, James R., Peters, Rex B.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): HORTON, KENNETH
• Application Number:
  US07/988,591
• Time in Patent Office: 861 Days
• Field of Search: 73/517 R, 73/517 B, 156/628, 156/648, 156/649, 156/662, 437/228, 437/901
• US Class Current: 438/584
• CPC Class Codes: C25F 3/12 of semiconducting materials

Abstract

A method for selectively etching a semiconductor wafer in the presence of an electrochemical etchant wherein the electrical potential of the area that is selectively etched is automatically changed to a potential at which the etching is inhibited once the desired etching in the area is completed. The method is described with respect to making an electrode tip for a tunnel current sensing device.

Claims

1. A method for selectively etching an area of a semiconductor wafer comprising the steps of:

holding said area of said semiconductor wafer at a first voltage potential at which an etchant will freely etch said area;

subjecting said semiconductor wafer to said etchant to etch said area;

automatically causing said area to approach a second voltage potential once said etching of said area is completed, said second voltage potential being at a potential which inhibits further etching of said area by said etchant, including providing first and second conductive paths to said area, said first conductive path being maintained at said first voltage potential, said second conductive path including a resistor, said second conductive path being connected to said second voltage potential to supply said second voltage potential to said area through said resistor; and

allowing said etchant to etch said area to disconnect said area from said first conductive path thereby allowing the potential of said area to approach said second voltage potential.

2. A method for selectively etching a semiconductor wafer comprising the steps of:

providing a first conductive path to a first region of an area of said semiconductor wafer that is to be selectively etched;

providing a second conductive path to a second region of said area of said semiconductor wafer, said second conductive path including a resistor;

maintaining said first conductive path at a first voltage potential, said first voltage potential being at a potential which allows an etchant to freely etch said semiconductor wafer; and

connecting said second conductive path to a second voltage potential, said second voltage potential being at a potential with respect to said etchant which inhibits the etch rate of said etchant, said second voltage potential being supplied to said second region of said area through said resistor;

subjecting said semiconductor wafer to said etchant to undercut said area of said semiconductor wafer in said first region to disconnect said area of said semiconductor wafer from said first conductive path and thereby allow the potential of said area to approach said second voltage potential and inhibit further etching by said etchant.

3. A method as claimed in claim 2 wherein said step of providing a first conductive path comprises the steps of:

providing said semiconductor wafer as a doped silicon substrate having an oppositely doped epitaxial layer;

etching said epitaxial layer to form an island of epitaxy, said first region being disposed on said island;

depositing an insulating layer over said semiconductor wafer while leaving said first region free of said insulating layer; and

forming a patterned metallization layer on said semiconductor wafer as said first conductive path, said patterned metallization layer electrically contacting said island at said first region.

4. A method as claimed in claim 3 wherein said step of forming a patterned metallization layer comprises the steps of:

forming a bus bar;

forming a branch strip that extends from said bus bar;

forming a substantially square metallization pad and an anchor pad on said island; and

forming first and second support strips, said first support strip connecting said branch strip to said substantially square metallization pad, said second support strip connecting said anchor pad to said substantially square metallization pad.

5. A method as claimed in claim 2 wherein said step of providing a second conductive path comprises the steps of:

providing said semiconductor wafer as a doped silicon substrate having an oppositely doped epitaxial layer;

etching said epitaxial layer to form an island of epitaxy, said second region being disposed on said island;

depositing an insulating layer over said semiconductor wafer while leaving said second region free of said insulating layer; and

forming a patterned metallization layer on said semiconductor wafer as said second conductive path, said patterned metallization layer electrically contacting said island at said second region.

6. A method as claimed in claim 5 wherein said step of forming a patterned metallization layer comprises the steps of:

forming a bus bar;

forming a branch strip that extends from said bus bar, said branch strip including said resistor; and

forming a metallization pad connected to said branch strip, said metallization pad making electrical contact with said second region on said island.

7. A method as claimed in claim 2 wherein the step of subjecting said semiconductor wafer to said etchant is further defined by subjecting said semiconductor wafer to a KOH etchant.

8. A method as claimed in claim 7 wherein the step of connecting said second conductive path to a second voltage potential is further defined by connecting said second conductive path to a second voltage potential which is positive with respect to said KOH etchant.

9. A method for making a tip for a tunnel current device comprising the steps of:

providing a first conductive path to a first region of an area of said semiconductor wafer that is to be selectively etched to make said tip;

providing a second conductive path to a second region of said area of said semiconductor wafer, said second conductive path including a resistor;

maintaining said first conductive path at a first voltage potential, said first voltage potential being at a potential which allows an etchant that is to be used to freely etch said semiconductor wafer to make said electrode tip;

connecting said second conductive path to a second voltage potential through a resistance, said second voltage potential being at a potential with respect to said etchant which inhibits the etch rate of said etchant; and

subjecting said semiconductor wafer to said etchant to undercut said area of said semiconductor wafer in said first region to form said electrode tip and disconnect said area of said semiconductor wafer from said first conductive path upon complete formation of said tip thereby allowing the potential of said area to approach said second voltage potential and inhibit further etching of said electrode tip by said etchant.

10. A method as claimed in claim 9 wherein said step of providing a first conductive path comprises the steps of:

providing said semiconductor wafer as a doped silicon substrate having an oppositely doped epitaxial layer;

etching said epitaxial layer to form an island of epitaxy, said first region being disposed on said island;

depositing an insulating layer over said semiconductor wafer while leaving said first region free of said insulating layer; and

forming a patterned metallization layer on said semiconductor wafer as said first conductive path, said patterned metallization layer electrically contacting said island at said first region.

11. A method as claimed in claim 10 wherein said step of forming a patterned metallization layer comprises the steps of:

forming a bus bar;

forming a branch strip that extends from said bus bar;

forming a substantially square metallization pad and an anchor pad on said island; and

forming first and second support strips, said first support strip connecting said branch strip to said substantially square metallization pad, said second support strip connecting said anchor pad to said substantially square metallization pad.

12. A method as claimed in claim 9 wherein said step of providing a second conductive path comprises the steps of:

providing said semiconductor wafer as a doped silicon substrate having an oppositely doped epitaxial layer;

etching said epitaxial layer to form an island of epitaxy, said second region being disposed on said island;

depositing an insulating layer over said semiconductor wafer while leaving said second region free of said insulating layer; and

forming a patterned metallization layer on said semiconductor wafer as said second conductive path, said patterned metallization layer electrically contacting said island at said second region.

13. A method as claimed in claim 12 wherein said step of forming a patterned metallization layer comprises the steps of:

forming a bus bar;

forming a branch strip that extends from said bus bar, said branch strip including said resistor; and

forming a metallization pad connected to said branch strip, said metallization pad making electrical contact with said second region on said island.

14. A method as claimed in claim 9 wherein the step of subjecting said semiconductor wafer to said etchant is further defined by subjecting said semiconductor wafer to a KOH etchant.

15. A method as claimed in claim 14 wherein the step of connecting said second conductive path to a second voltage potential is further defined by connecting said second conductive path to a second voltage potential which is positive with respect to said KOH etchant.

16. A method for making a plurality of electrode tips for tunnel current devices on a semiconductor wafer comprising the steps of:

providing a semiconductor wafer having a doped substrate and an oppositely doped epitaxial layer;

etching said epitaxial layer of said semiconductor wafer to create an island for each electrode tip that is to be made;

providing an insulating layer to said semiconductor wafer except in respective first and second regions of each island;

providing a first conductive path to each said first region;

providing a second conductive path to each said second region, said second conductive path including a resistor respectively associated with each said second region;

maintaining said first conductive path at a first voltage potential, said first voltage potential being at a potential which allows an etchant that is to be used to freely etch each said tip;

connecting said second conductive path to a second voltage potential, said second voltage potential being at a potential with respect to said etchant which inhibits the etch rate of said etchant, said second voltage potential being supplied to each island through the associated resistor; and

subjecting said semiconductor wafer to said etchant to respectively undercut each said first region to form said electrode tip and to disconnect each said island from said first conductive path once etching of said electrode tip is completed thereby allowing the potential of each said island to approach said second voltage potential upon completion of the respective electrode tip.

17. A method as claimed in claim 16 wherein said step of providing a semiconductor wafer is further defined by providing a semiconductor wafer having a doped silicon substrate and an oppositely doped epitaxial layer.

18. A method as claimed in claim 16 wherein the step of subjecting said semiconductor wafer to said etchant is further defined by subjecting said semiconductor wafer to a KOH etchant.

19. A method as claimed in claim 18 wherein the step of connecting said second conductive path at a second voltage potential is further defined by maintaining said second conductive path at a second voltage potential which is positive with respect to said KOH etchant.