Circuit for driving two power mosfets in a half-bridge configuration
First Claim
1. A circuit for alternately driving first and second transistors, each transistor having a control terminal for receiving a transistor drive signal, at least one of the transistors having a terminal coupled to an output terminal adapted to be coupled to a load, the circuit comprising:
- a driver input adapted for receiving a driver input signal having a first state intended to turn the first transistor ON and the second transistor OFF, and a second state intended to turn the first transistor OFF and the second transistor ON;
means for monitoring the first transistor to generate a first signal indicative of the first transistor being in an operational state that can be considered substantially OFF;
means for monitoring the second transistor to generate a second signal indicative of the second transistor being in an operational state that can be considered substantially OFF;
means coupled to the control terminals of the first and second transistors for driving the transistors in response to the driver input signal, and to the first and second signals, so that (1) the first transistor is prevented from being driven ON until the driver input signal is in the first state and the second signal is also present, and (2) the second transistor is prevented from being driven ON until the driver input signal is in the second state and the first signal is also present; and
means for preventing a capacitively-induced transient signal from one of the first and second transistors from affecting the turning ON of the other transistor,whereby the drive to each of the first and second transistors is inhibited until the other transistor is considered to be substantially OFF.
3 Assignments
0 Petitions
Accused Products
Abstract
A driver circuit and method for alternately driving first and second power transistors is provided. The driver circuit includes shoot-through reduction circuitry for monitoring the gate-to-source voltages of the two power transistors so as to inhibit the turning-ON of each power transistor until the gate-to-source voltage of the other power transistor has fallen to a voltage level indicative of the other transistor being OFF. Additionally, the driver circuit includes a circuit to prevent transient signals from said power transistors from affecting the operation of the driver circuit.
148 Citations
53 Claims
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1. A circuit for alternately driving first and second transistors, each transistor having a control terminal for receiving a transistor drive signal, at least one of the transistors having a terminal coupled to an output terminal adapted to be coupled to a load, the circuit comprising:
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a driver input adapted for receiving a driver input signal having a first state intended to turn the first transistor ON and the second transistor OFF, and a second state intended to turn the first transistor OFF and the second transistor ON; means for monitoring the first transistor to generate a first signal indicative of the first transistor being in an operational state that can be considered substantially OFF; means for monitoring the second transistor to generate a second signal indicative of the second transistor being in an operational state that can be considered substantially OFF; means coupled to the control terminals of the first and second transistors for driving the transistors in response to the driver input signal, and to the first and second signals, so that (1) the first transistor is prevented from being driven ON until the driver input signal is in the first state and the second signal is also present, and (2) the second transistor is prevented from being driven ON until the driver input signal is in the second state and the first signal is also present; and means for preventing a capacitively-induced transient signal from one of the first and second transistors from affecting the turning ON of the other transistor, whereby the drive to each of the first and second transistors is inhibited until the other transistor is considered to be substantially OFF. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A circuit for alternately driving first and second transistors, each transistor having a control terminal for receiving a transistor drive signal, at least one of the transistors having a terminal coupled to an output terminal adapted to be coupled to a load, the circuit comprising:
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a driver input adapted for receiving a driver input signal having a first state intended to turn the first transistor ON and the second transistor OFF, and a second state intended to turn the first transistor OFF and the second transistor ON; a first circuit coupled to the first transistor to monitor the first transistor and generate a first signal indicative of the first transistor being in an operational state that can be considered substantially OFF; a second circuit coupled to the second transistor to monitor the second transistor and generate a second signal indicative of the second transistor being in an operational state that can be considered substantially OFF; a third circuit coupled to the control terminals of the first and second transistors for driving the transistors in response to the driver input signal, and to the first and second signals, so that (1) the first transistor is prevented from being driven ON until the driver input signal is in the first state and the second signal is also present, and (2) the second transistor is prevented from being driven ON until the driver input signal is in the second state and the first signal is also present; and a fourth circuit for preventing a capacitively-induced transient signal from one of the first and second transistors from affecting the turning ON of the other transistor, whereby the drive to each of the first and second transistors is inhibited until the other transistor is considered to be substantially OFF. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A circuit for alternately driving first and second transistors, each transistor having a control terminal for receiving a transistor drive signal, at least one of the transistors having a terminal coupled to an output terminal adapted to be coupled to a load, the circuit adapted for receiving a driver input signal having a first state intended to turn the first transistor ON and the second transistor OFF, and a second state intended to turn the first transistor OFF and the second transistor ON, the driver circuit comprising:
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means for generating a first signal responsive to a determination that the first transistor has entered an operational state that can be considered substantially OFF; means for generating a second signal responsive to a determination that the second transistor has entered an operational state that can be considered substantially OFF; means coupled to the control terminals of the first and second transistors for driving the transistors in response to the driver input signal, and to the first and second signals, so that (1) the first transistor is prevented from being driven ON until the driver input signal is in the first state and the second signal is also present, and (2) the second transistor is prevented from being driven ON until the driver input signal is in the second state and the first signal is also present; and means for preventing a capacitively-induced transient signal from one of the first and second transistors from affecting the turning ON of the other transistor, whereby the drive to each of the first and second transistors is inhibited until the other transistor is considered to be substantially OFF. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A circuit for alternately driving first and second transistors, each transistor having a control terminal for receiving a transistor drive signal, at least one of the transistors having a terminal coupled to an output terminal adapted to be coupled to a load, the circuit adapted for receiving a driver input signal having a first state intended to turn the first transistor ON and the second transistor OFF, and a second state intended to turn the first transistor OFF and the second transistor ON, the driver circuit comprising:
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a first circuit coupled to the first transistor for generating a first signal responsive to a determination that the first transistor has entered an operational state that can be considered substantially OFF; a second circuit coupled to the second transistor for generating a second signal responsive to a determination that the second transistor has entered an operational state that can be considered substantially OFF; third circuit coupled to the control terminals of the first and second transistors for driving the transistors in response to the driver input signal, and to the first and second signals, so that (1) the first transistor is prevented from being driven ON until the driver input signal is in the first state and the second signal is also present, and (2) the second transistor is prevented from being driven ON until the driver input signal is in the second state and the first signal is also present; and a fourth circuit for preventing a capacitively-induced transient signal from one of the first and second transistors from affecting the turning ON of the other transistor, whereby the drive to each of the first and second transistors is inhibited until the other transistor is considered to be substantially OFF. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42)
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43. A method for alternately driving first and second transistors, each transistor having a control terminal for receiving a transistor drive signal, at least one of the transistors having a terminal coupled to an output terminal adapted to be coupled to a load, the circuit adapted for receiving a driver input signal having a first state intended to turn the first transistor ON and the second transistor OFF, and a second state intended to turn the first transistor OFF and the second transistor ON, the method comprising the steps of:
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(a) detecting when the first transistor is in an operational state that can be considered substantially OFF to responsively generate a first signal; (b) detecting when the second transistor is in an operational state that can be considered substantially OFF to responsively generate a second signal; (c) preventing the first transistor from being driven ON until the driver input signal is in the first state and the second signal is also present, and preventing the second transistor from being driven ON until the driver input signal is in the second state and the first signal is also present; and (d) preventing a capacitively-induced transient signal from one of the first and second transistors from affecting the turning ON of the other transistor, whereby the drive to each of the first and second transistors is inhibited until the other transistor is considered to be substantially OFF. - View Dependent Claims (44, 45, 46, 47, 48, 49)
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50. A circuit for alternately driving first and second transistors, each transistor having a control terminal for receiving a transistor drive signal, at least one of the transistors having a terminal coupled to an output terminal adapted to be coupled to a load, the circuit comprising:
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a driver input adapted for receiving a driver input signal having a first state intended to turn the first transistor ON and the second transistor OFF, and a second state intended to turn the first transistor OFF and the second transistor ON; a first circuit for monitoring the first transistor to generate an "OFF" signal indicative of that transistor being in an operational state that can be considered substantially OFF; a second circuit coupled to the control terminals of the first and second transistors for driving the transistors in response to the driver input signal and to the "OFF" signal, so that the second transistor is prevented from being driven ON until the driver input signal is in the second state and the "OFF" signal is also present; and a third circuit for preventing a capacitively-induced transient signal from one of the first transistor from affecting the turning ON of the second transistor, whereby the drive to the second transistor is inhibited until the first transistor is considered to be substantially OFF. - View Dependent Claims (51, 52, 53)
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Specification