Second order Sigma-Delta based analog to digital converter having superior analog components and having a programmable comb filter coupled to the digital signal processor

• US 5,408,235 A
• Filed: 03/07/1994
• Issued: 04/18/1995
• Est. Priority Date: 03/07/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Beatty, Tim, Liepold, Carl F., Doyle, James T.
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US08/207,040
• Time in Patent Office: 407 Days
• Field of Search: 341/143, 341/155, 341/118, 341/120, 364/724.1, 375/26
• US Class Current: 341/143
• CPC Class Codes: H03H 17/0251 Comb filters
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
• CPC Class Codes: H03M 3/462 Details relating to the decimation process decimation filters in general H03H17/0416, H03H17/0621

Abstract

A "true" 16-bit second order Sigma-Delta based converter that has superior analog components and has a programmable comb filter which is coupled to the digital signal processor. This converter comprises a second order Sigma-Delta modulator and a programmable comb filter. The second order Sigma-Delta modulator dramatically attenuates the baseband quantization noise energy (which in turn increases the resolution of the converter), since its superior amplifiers and comparators enable it to oversample and coarsely quantize the analog input signal at a very high sampling frequency of 12 MHz. The amplifiers are class AB OTAs, which have cross coupled NMOS driven input stages, and cascoded output stages. Also, the common mode voltages are the optimal biasing points, and these voltages are kept constant by a differential input stage, by a PV independent temperature dependent current generator, by optimal device size, and by a common mode feedback circuitry. The programmable comb filter receives the coarsely digitized 1-bit output of the modulator at oversampling frequency F_S, and provides a more accurate representation of the input signal to the DSP at slower sampling rate of F_S /N. In addition, the comb filter uses a 20-bit data path, in order to enable the decimator (which is formed by the comb filter and by the FIR filter) to provide 16 bits of resolution to the DSP. The output of the programmable comb filter is then supplied to an FIR filter which is realized in the DSP, and this filter removes the remaining out-of-baseband noise.

Claims

1. An oversampling analog to digital converter, for converting an input signal having a baseband frequency into an output set of high resolution samples having an output frequency and representing said input signal, comprising:

(a) a Sigma-Delta modulator for (i) receiving, from a clock pulse generator, an oversampling clock signal having an oversampling frequency, (ii) receiving said input signal, and (iii) sampling said input signal at said oversampling frequency and producing a first set of coarsely quantized samples having said oversampling frequency and representing said input signal, wherein said oversampling attenuates quantization noise in the frequency range from DC to said basedband frequency while increasing quantization noise for frequencies greater than said baseband frequency; and

(b) a digital filter for (i) receiving said oversampling clock signal, (ii) receiving said first set of samples from said modulator, and (iii) computing a first weighted average of an adjustable number of samples in said first set of samples, and thereby producing a second set of samples representing said input signal and having a second sampling frequency equal to said oversampling frequency divided by said adjustable number of samples used in computing said first weighted average, wherein said weighted averaging attenuates quantization noise for frequencies greater than said baseband frequency.

2. The oversampling analog to digital converter of claim 1, wherein said digital filter is a programmable primary comb filter comprising a predetermined number (K) of cascaded secondary comb filters, wherein said first set of samples arrive at said primary comb filter a predetermined number of bits (Bi) at a time, said adjustable number is at most equal to a predetermined maximum number (M), and said primary comb filter has a minimum number of bit paths (W) equal to K*log₂ (M)+Bi.

3. The oversampling analog to digital converter of claim 2 further comprising a second digital filter for (i) receiving said oversampling clock signal, (ii) receiving said second set of samples from said first digital filter, and (iii) computing a second weighted average of a predetermined number of samples in said second set of samples and thereby producing said output set of high resolution samples.

4. The oversampling analog to digital converter of claim 3, wherein said second digital filter is realized in a digital signal processor having at least one processor that receives said output set of high resolution samples from said second digital filter.

5. The oversampling analog to digital converter of claim 4, wherein said second digital filter is a Finite Impulse Response (FIR) filter.

6. The oversampling analog to digital converter of claim 5, wherein said Sigma-Delta modulator is a second order Sigma-Delta modulator, said primary comb filter is a third order comb filter having at least 19 bit paths, and said secondary comb filters are first order comb filters.

7. The oversampling analog to digital converter of claim 5, wherein said FIR filter comprises a first half-band filter and a second half-band filter, wherein said first half-band filter is a Goodman filter.

8. The oversampling analog to digital converter of claim 3, coupled to a high speed analog to digital converter, for calibrating a calibrator of said high speed analog to digital converter.

9. A Sigma-Delta modulator, for oversampling and coarsely quantizing an input signal, comprising:

at least one sampler operating at an oversampling frequency for converting said input signal into a first set of digital signals;

at least one transforming circuit for transforming said first set of digital signals into a second set of digital signals; and

at least one integrator receiving said second set of digital signals and having a differential class AB operational transconductance amplifier (OTA) capable of processing digital signals at said oversampling frequency;

wherein said OTA includes

a differential cross-coupled input stage, driven by N-channel MOS transistors and having a plurality of input currents, for receiving said second set of digital signals,

a first biasing stage having a plurality of biasing currents for establishing and maintaining the optimal biasing points of said OTA, wherein said optimal biasing maximize the linear range of operation of said OTA,

a differential output stage driven by said input stage, wherein said input currents are mirrored into said output stage to produce a plurality of output currents,

a dynamic biasing stage, coupled to said input and output stages, for dynamically biasing said output stage,

a common mode feedback stage, coupled to said differential output stage and using switch capacitor sampling techniques, for establishing and maintaining the optimal biasing points of said OTA, and

common mode feedback disabling circuitry for disabling said common mode feedback stage, thereby enabling said OTA to operate continuously.

10. The Sigma-Delta modulator of claim 9, wherein said optimal biasing points are further established and maintained by a current generator establishing the biasing currents in said OTA by producing at least one reference current and mirroring said reference current into said biasing stage, wherein said biasing currents establish and maintain said biasing points to be independent of transistor conductance parameter variations, operating temperature variations, and power supply variations.

11. The Sigma-Delta modulator of claim 10, wherein said reference current and said biasing currents are independent of process and power supply variations, while being slightly dependent on variations in operating temperature so as to offset the effects due to operating temperature variations on the optimal biasing points of said OTA.

12. The Sigma-Delta modulator of claim 11, wherein said current generator uses a Bandgap Reference technique to establish a voltage across a resistor, wherein said voltage is independent of power supply variations and transistor conductance parameter variations.

13. The Sigma-Delta modulator of claim 12, wherein said current generator uses a Proportional To Absolute Temperature (PTAT) technique to establish the desired temperature dependence of said reference current and said biasing currents.

14. The Sigma-Delta modulator of claim 13, wherein said current generator comprises a generating stage and an output stage, wherein said generating stage includes:

an operational amplifier having a negative input terminal, a positive input terminal, and an output terminal, wherein a first biasing voltage appears at the output terminal of said operational amplifier,

said resistor having a first terminal coupled to said positive input terminal of said operational amplifier and a second terminal,

at least a first MOS transistor and a second MOS transistor, each MOS transistor having a first terminal, a second terminal, and a third terminal, wherein said first terminals of said MOS transistors are coupled to a first supply voltage, said second terminals of said MOS transistors are coupled to said output terminal of said amplifier, and said third terminal of said first MOS transistor is coupled to said first terminal of said resistor,

at least a first and a second parasitic bipolar junction transistors, each having a collector, a base, and an emitter, wherein said emitter of said second bipolar junction transistor has a larger area than the emitter of said first bipolar junction transistor, wherein said bases and said emitters of said bipolar junction transistor are coupled to a second supply voltage, said collector of said first bipolar junction transistor is coupled to said second terminal of said resistor, and said collector of said second bipolar transistor is coupled to the third terminal of said second MOS transistor and to said negative input terminal of said operational amplifier,

wherein said output stage includes a third MOS transistor and a fourth MOS transistor each having a first terminal, a second terminal, and a third terminal, wherein said reference current flows through said output stage and is generated by coupling the second terminal of said third MOS transistor with said output terminal of said operational amplifier, wherein said third terminal of said third MOS transistor is coupled to said first supply voltage, said first terminal of said third MOS transistor is coupled to said first and second terminal of said fourth MOS, and said third terminal of said fourth MOS is coupled to said second supply voltage.

15. The Sigma-Delta modulator of claim 9, wherein said OTA further comprises a plurality of P-channel MOS transistors each having a source and a body, wherein each of said P-channel MOS transistors has its body coupled to its source.

16. The Sigma-Delta modulator of claim 9 further comprising a level shifted comparator coupled to said integrator and having an input stage and an output stage, wherein said input stage of said comparator is level shifted so that the trip points of said comparator are close to the biasing points of said OTA.