Semiconductor memory with inhibited test mode entry during power-up

• US 5,408,435 A
• Filed: 11/20/1992
• Issued: 04/18/1995
• Est. Priority Date: 08/17/1990
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Coker, Thomas A., McClure, David C.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Lane, Jack
• Application Number:
  US07/984,233
• Time in Patent Office: 879 Days
• Field of Search: 365/195, 365/201, 365/226, 365/227, 365/228, 365/233, 365/233.5, 371/21.1, 371/21.2, 371/66, 307/443, 307/465, 395/425, 364/DIG. 1, 364/DIG. 2
• US Class Current: 365/201
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Claims

1. An integrated circuit having a normal operating mode and a test mode, said test mode being a special operating mode in which the operation of the integrated circuit is evaluated internally to the integrated circuit and in which normal operation of the integrated circuit is disabled, comprising:

a power supply terminal for receiving a power supply voltage for biasing said circuit;

a first terminal for receiving a mode initiate signal indicating selection of said test mode;

a power-on reset circuit for detecting the voltage of said power supply at said power supply terminal, said power-on reset circuit having an output for presenting a signal indicating with a first state that the voltage of said power supply is below a threshold level; and

an enable circuit, coupled to said first terminal and to said power-on reset circuit, for generating an enabling signal for said test mode responsive to receipt of said mode initiate signal at said first terminal, said enable circuit also for not generating the enabling signal responsive to receipt of the first state of said signal at the output of said power-on reset circuit in combination with receipt of said mode initiate signal at said first terminal, comprising;

a latch, having a reset input for receiving the signal from said power-on reset circuit so that said latch is reset responsive to said signal from said power-on reset circuit being at said first state, and having a data input receiving the mode initiate signal at said first terminal;

wherein the state of said latch determines the state at the output of said enable circuit so that, when said latch is reset, the output of said enable circuit presents a signal selecting the normal operating mode.

2. The integrated circuit of claim 1, wherein said power-on reset circuit is also for presenting at its output a signal indicating with a second state that the voltage of said power supply is above said threshold level.

3. The integrated circuit of claim 2, wherein said enabling circuit generates said enable signal responsive to receipt of said mode initiate signal at said first terminal in combination with receipt of said signal from said power-on reset circuit indicating that the voltage of said power supply is above said threshold level.

4. The integrated circuit of claim 1, wherein said enable circuit further comprises:

an overvoltage detection circuit for communicating a data state to said latch responsive to detecting an overvoltage excursion at said first terminal;

wherein said overvoltage excursion at said first terminal corresponds to said mode initiate signal.

5. The integrated circuit of claim 4, wherein said overvoltage detection circuit is disabled from detecting an overvoltage excursion responsive to said power-on reset circuit presenting a signal at said first state.

6. The integrated circuit of claim 1, wherein said enable circuit further comprises:

evaluation logic for presenting a data state to said latch responsive to a logic state at said first terminal;

wherein the logic state at said first terminal corresponds to said mode initiate signal.

7. The integrated circuit of claim 1, further comprising:

a second terminal, for receiving a selection code;

wherein said enable circuit comprises;

an overvoltage detection circuit for detecting an overvoltage excursion at said first terminal; and

evaluation logic for presenting a data state to said latch responsive to the selection code received at said second terminal and responsive to said overvoltage detection circuit;

and wherein said selection code at said second terminal at the time of an overvoltage excursion at said terminal corresponds to said mode initiate signal.

8. The integrated circuit of claim 1, wherein upon power-up of the voltage at said power supply terminal, said latch enters a state corresponding to selection of the normal operating mode.

9. An integrated circuit having a normal operating mode and a test mode, said test mode being a special operating mode in which the operation of the integrated circuit is evaluated internally to the integrated circuit and in which normal operation of the integrated circuit is disabled, comprising:

a power supply terminal for receiving a power supply voltage for biasing said circuit;

a first terminal for receiving a mode initiate signal indicating selection of said test mode;

a power-on reset circuit for detecting the voltage of said power supply at said power supply terminal, said power-on reset circuit having an output for presenting a signal indicating with a first state that the voltage of said power supply is below a threshold level; and

an enable circuit, coupled to said first terminal and to said power-on reset circuit, for generating an enabling signal for said test mode responsive to receipt of said mode initiate signal at said first terminal, said enable circuit also for not generating the enabling signal responsive to receipt of the first state of said signal at the output of said power-on reset circuit in combination with receipt of said mode initiate signal at said first terminal, comprising;

a plurality of latches connected sequentially;

wherein a first one of said plurality of latches has a data input receiving the state of said first terminal;

wherein the state of a last one of said plurality of latches determines the state at the output of said enable circuit;

and wherein each of said plurality of latches has a reset input for receiving the signal from an output of said power-on reset circuit so that each of said plurality of latches is reset responsive to the signal from the power-on reset circuit being at said first state, such reset of each of said plurality of latches causing the output of said enable circuit to present a signal selecting the normal operating mode.

10. A method for controlling an enabling of a test mode in an integrated circuit having a normal operating mode and the test mode, the test mode being a special operating mode in which the operation of the integrated circuit is evaluated internally to the integrated circuit and in which normal operation of the integrated circuit is disabled, comprising:

monitoring a power supply voltage to determine if the power supply voltage is above or below a threshold value;

receiving a test mode initiate signal;

generating a test mode enable signal responsive to the test mode initiate signal if the power supply voltage is above the threshold value by clocking a latch and by driving the test mode enable signal from an output of the latch;

.

communicating the test mode enable signal to portions of the integrated circuit so that the test mode is enabled; and

inhibiting the generation of the test mode enable signal responsive to the test mode initiate signal if the power supply voltage is below the threshold value by resetting the latch, responsive to detecting that the power supply voltage is below the threshold value.

11. The method of claim 10, further comprising:

setting said latch upon power-up of said power supply to a state where said test mode enable signal is not driven from its output.

12. The method of claim 10, wherein said step of receiving the test mode initiate signal comprises:

detecting an overvoltage condition at a terminal.

13. The method of claim 12, further comprising:

inhibiting the detecting of an overvoltage condition at said terminal responsive to detecting that the power supply voltage is below said threshold value.