Computer graphics system with parallel processing using a switch structure

• US 5,408,606 A
• Filed: 01/07/1993
• Issued: 04/18/1995
• Est. Priority Date: 01/07/1993
• Status: Expired due to Term

• Current Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Original Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Inventors: Eckart, Glen A.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): Tung, Kee M.
• Application Number:
  US08/001,441
• Time in Patent Office: 831 Days
• Field of Search: 395/162-166, 395/121, 395/122, 395/126, 395/133, 395/134, 395/138, 395/139, 395/325
• US Class Current: 345/505
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

Front end processors in a graphics architecture execute parallel scan conversion and shading to first process individually assigned primitive objects for providing update pixels. A crossbar accommodates data rearrangement whereby parallel pixel processors with associated memory capabilities (frame buffer banks) perform visibility and blending operations on predetermined sequences of update pixels to provide display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines or distributed over an area. Specific distribution criteria are disclosed for patterns. One form of pixel processor organization incorporates a distributed frame buffer with FIFO memory and control stacks. Display pixels are received by a multiplexer to supply a digital-analog connector with display data in raster sequence.

Claims

1. A graphics system for processing primitive data, as from a host computer, to provide display data in the form of display pixels related to locations in a display, said graphics system comprising:

a structure for processing said primitive data to provide representative update pixels related to the locations in said display;

a plurality of visibility-and-blend processors, said visibility-and-blend processors each including an associated frame buffer bank, the frame buffer banks collectively defining a composite frame buffer, each frame buffer bank for storing predetermined frame buffer pixels that are spaced apart and in sequence skipping locations of said display, said plurality of visibility-and-blend processors each for iteratively processing said update pixels in said associated frame buffer bank; and

a switch structure for supplying said update pixels to said plurality of visibility-and-blend processors in accordance with said sequence skipping locations of said display.

2. A system according to claim 1 wherein said structure for processing said primitive data comprises a plurality of primitive processors for iteratively receiving and processing the primitive data for individual primitives.

3. A system according to claim 2 wherein said primitive processors receive primitive coherent data, said plurality of visibility-and-blend processors receive screen space coherent data.

4. A system according to claim 3 further including a display unit coupled to receive display sequence data.

5. A system according to claim 3 further including a pixel multiplexer for receiving frame buffer pixels from said frame buffer banks to provide said display pixels in a display sequence according to a raster pattern.

6. A system according to claim 1 wherein said structure for processing said primitive data includes means for scan converting said primitive data.

7. A system according to claim 6 wherein said structure for processing said primitive data further includes means for shading said primitive data.

8. A system according to claim 1 wherein said plurality of visibility-and-blend processors determine visibility between said update pixels and content of said associated frame buffer bank to resolve contention.

9. A system according to claim 1 wherein said plurality of visibility-and-blend processors further include FIFOs for storing pixel data.

10. A system according to claim 1 further including a display pixel multiplexer for receiving display pixels from said frame buffer banks to provide said display pixels in a display sequence.

11. A system according to claim 10 wherein said display sequence is a raster pattern.

12. A system according to claim 1 wherein said sequence skipping locations are related to a raster scan pattern.

13. A system according to claim 1 wherein said sequence skipping locations are specified in line raster numerical sequence with skip voids between lines.

14. A system according to claim 13 wherein said frame buffer pixels are addressed to said frame buffer banks in accordance with the following:

address of frame buffer bank as related to a numerical sequence raster scan=(y·

X_SC +x) mod_n where;

y=raster line,

x=pixel in line,

X_SC =length of scan line, and

n=number of banks

15. A system according to claim 13 wherein said frame buffer pixels are addressed to said frame buffer banks in accordance with the following:

address in said frame buffer banks as related to a numerical sequence raster scan=(y·

X_SC +x)div_n where;

y=raster line,

x=pixel in line,

X_SC =length of scan line, and

n=number of banks.