Processor with multiple microprogrammed processing units

• US 5,408,623 A
• Filed: 09/27/1993
• Issued: 04/18/1995
• Est. Priority Date: 11/30/1989
• Status: Expired due to Term

• Current Assignee: Bull Sas (Atos SE)
• Original Assignee: Bull Sas (Atos SE)
• Inventors: Franzetti, Hubert, Vallet, Philippe, Vinot, Annie, Dolidon, Thierry, Lamarche, Marie-Odile
• Primary Examiner(s): Harrell, Robert B.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/127,124
• Time in Patent Office: 568 Days
• Field of Search: 395/325, 395/375, 395/800
• US Class Current: 712/248
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A data processing system having processors with large instruction sets comprises a plurality of microprogrammed execution units (EAD, BDP, FPP), which communicate with one another and with a memory (MU) by way of a cache memory (CA). One of the units is an addressing unit (EAD). A second unit is a binary and a decimal calculation unit (BOP). A third unit is a floating point calculation unit (FPP). To permit the units to function autonomously, each unit includes its own command block and synchronizing means to authorize or interrupt the execution of the microprogram defined by the instruction in progress in each unit. These synchronizing means interrupt said execution if:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result.

Claims

1. A processor for a data processing system including a plurality of microprogrammed processing units (U₁, U₂, U₃), each of said processing units being particularly adapted to execute a complementary subset of functions of the processor, wherein the subset of functions of each processing unit complements the subset of functions of the remaining processing units to define a complete set of functions of the processor in a manner which enables pipeline execution of instructions by said processor, said units being connected to memory means (CA) containing program instructions to be executed and operands, at least one of said units being an addressing unit (EAD) for addressing said memory means (CA) to obtain the instructions and the operands, said processor being characterized in that said units (U₁, U₂, U₃) include command block means (1) for decoding the instructions furnished by the memory means (CA) and autonomously executing functions defined by said instructions, each unit further including synchronizing means (15, 16, 17, 18, 19) for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit, said synchronizing means being adapted to interrupt (NOEX) said execution when:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memorizing means intended to receive said result.

2. The processor of claim 1, wherein said memory means (CA) includes interface means (ICU) connected to a first operand bus (OPE), and a second result bus (RES), said first and second buses serving respectively to read the operands and write the results into said memory means (CA);

each unit (U₁, U₂, U₃) being connected respectively via a first and second interface to said operand bus (OPE) and result bus (RES);

each unit (U1, U2, U3) further including first means (3) for receiving and detecting a first indicator of ownership (OPE-OWN) associated with the operand bus (OPE) and first sending means (3a) for sending to the other units said first indicator of ownership (OPE-OWN);

each unit further including second means (3) for receiving and detecting a second indicator of ownership (RES-OWN) associated with the result bus (RES) and second sending means (3b) for sending to the other unit said second indicator of ownership (RES-OWN); and

said units are connected to one another via first and second control links (CD-OPE, CD-RES) respectively enabling the sending of said first and second indicators;

such that one of the conditions of effective reception of an operand by a unit is the detection by said unit of said first indicator (OPE-OWN); and

one of the conditions of effective sending of a result by a unit is the detection in said unit of said second indicator (RES-OWN).

3. The processor of claim 2, wherein said memory means (CA) are connected to said units via operand sending notification links associated with the operand bus (OPE) and include means for transmitting operand sending signals (SEND) over these links when said memory means send an operand, and each unit further including means (3) for receiving and detecting said operand sending signals, and being characterized in that another condition of effective reception of an operand by a unit is the detection by said unit of an expected sending signal (SEND).

4. The processor of claim 3, wherein said units are connected to said memory means (CA) via reception acknowledgement links associated with the operand bus (OPE), and each unit including means (3) for sending over said reception acknowledgement links a signal of reception acknowledgement (GOT) when an operand is effectively received by said unit in such a way as to inform said memory means (CA) of receipt of the operand.

8. The processor of claim 2, wherein said units are connected to one another by links associated with the result bus (RES) for notifying that a result has been sent, said units including owner unit means for exchanging result sending signals (RES-CP) and addressee signals (DEST) over said links, said result sending signals (RES-CP) and said addressee signals (DEST) being sent by the owner unit means when said owner unit means sends data over the result bus (RES) to the unit identified by said addressee signals (DEST);

and being characterized in that the condition of effective reception of a result by a unit is the detection of a result sending signal (RES-CP) and the coincidence of said addressee signals with the identity of said unit.

10. The processor of claim 4, wherein said units are connected to one another by links associated with the result bus (RES) notifying that a result has been sent for said units including owner unit means for exchanging result sending signals (RES-CP) and addressee signals (DEST) over said links, said result sending signals (RES-CP) and said addressee signals (DEST) being sent by the owner unit means when said owner unit means sends data over the result bus (RES) to the unit identified by said addressee signals (DEST);

and being characterized in that the condition of effective reception of a result by a unit is the detection of a result sending signal (RES-CP) and the coincidence of said addressee signals with the identity of said unit.

12. The processor of claim 2, wherein each unit includes a command block and the respective ownerships (OPE-OWN, RES-OWN) of the operand bus (OPE) and result bus (RES) at the beginning of execution of the microprogram of the instruction in progress are determined by the command block of each unit as a function of the operating code of said instructions;

and said ownerships being capable of modification during the execution of said microprogram by the owner unit means of said operand and result buses (OPE, RES).

13. The processor of claim 3, wherein each unit includes a command block and the respective ownerships (OPE-OWN, RES-OWN) of the operand bus (OPE) and result bus (RES) at the beginning of execution of the microprogram of the instruction in progress are determined by the command block of each unit as a function of the operating code of said instructions;

and said ownerships being capable of modification during the execution of said microprogram by the owner unit means of said operand and result buses (OPE, RES).

14. The processor of claim 4, wherein each unit includes a command block and the respective ownerships (OPE-OWN, RES-OWN) of the operand bus (OPE) and result bus (RES) at the beginning of execution of the microprogram of the instruction in progress are determined by the command block of each unit as a function of the operating code of said instructions;

and said ownerships being capable of modification during the execution of said microprogram by the owner unit means of said operand and result buses (OPE, RES).

19. The processor of claim 2, wherein each unit includes means (15, 19) for suspending execution of the microprogram in progress in each unit upon the detection of a conditional transfer of control microinstruction, the calculation of which is not performed by said unit, said units being connected to one another by an algorithm link (ALGO) enabling the unit that calculates the conditional transfer of control the transmit the results of said calculation to the other units, thus authorizing the continuation of the suspended microprograms in said other units.

20. The processor of claim 3, wherein each unit includes means (15, 19) for suspending execution of the microprogram in progress in each unit upon the detection of a conditional transfer of control microinstruction, the calculation of which is not performed by said unit, said units being connected to one another by an algorithm link (ALGO) enabling the unit that calculates the conditional transfer of control the transmit the results of said calculation to the other units, thus authorizing the continuation of the suspended microprograms in said other units.

21. The processor of claim 4, wherein each unit includes means (15, 19) for suspending execution of the microprogram in progress in each unit upon the detection of a conditional transfer of control microinstruction, the calculation of which is not performed by said unit, said units being connected to one another by an algorithm link (ALGO) enabling the unit that calculates the conditional transfer of control the transmit the results of said calculation to the other units, thus authorizing the continuation of the suspended microprograms in said other units.

23. The processor of claim 8, wherein each unit includes means (15, 19) for suspending execution of the microprogram in progress in each unit upon the detection of a conditional transfer of control microinstruction, the calculation of which is not performed by said unit, said units being connected to one another by an algorithm link (ALGO) enabling the unit that calculates the conditional transfer of control the transmit the results of said calculation to the other units, thus authorizing the continuation of the suspended microprograms in said other units.

24. The processor of claim 12, wherein each unit includes means (15, 19) for suspending execution of the microprogram in progress in each unit upon the detection of a conditional transfer of control microinstruction, the calculation of which is not performed by said unit, said units being connected to one another by an algorithm link (ALGO) enabling the unit that calculates the conditional transfer of control the transmit the results of said calculation to the other units, thus authorizing the continuation of the suspended microprograms in said other units.

25. The processor of claim 2, wherein said memory means (CA) comprise a cache memory, and said interface means (ICU) of said cache memory includes at least two independent buffers (OB1, OB2) connected at the input to the result bus (RES) and to the cache memory, and connected at the output to the operand bus (OPE) and to the cache memory.

26. The processor of claim 3, wherein said memory means (CA) comprise a cache memory, and said interface means (ICU) of said cache memory includes at least two independent buffers (OB1, OB2) connected at the input to the result bus (RES) and to the cache memory, and connected at the output to the operand bus (OPE) and to the cache memory.

27. The processor of claim 4, wherein said memory means (CA) comprise a cache memory, and said interface means (ICU) of said cache memory includes at least two independent buffers (OB1, OB2) connected at the input to the result bus (RES) and to the cache memory, and connected at the output to the operand bus (OPE) and to the cache memory.

29. The processor of claim 8, wherein said memory means (CA) comprise a cache memory, and said interface means (ICU) of said cache memory includes at least two independent buffers (OB1, OB2) connected at the input to the result bus (RES) and to the cache memory, and connected at the output to the operand bus (OPE) and to the cache memory.

30. The processor of claim 12, wherein said memory means (CA) comprise a cache memory, and said interface means (ICU) of said cache memory includes at least two independent buffers (OB1, OB2) connected at the input to the result bus (RES) and to the cache memory, and connected at the output to the operand bus (OPE) and to the cache memory.

32. The processor of claim 1, wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).

33. The processor of claim 2, wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).

34. The processor of claim 3, wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).

35. The processor of claim 4, wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).

37. The processor of claim 8, wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).

38. The processor of claim 12, wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).

39. The processor of claim 19, wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).

5. A processor for a data processing system including a plurality of microprogrammed processing units (U₁, U₂, U₃) sharing a set of functions of said processor, each unit being assigned the execution of a subset of functions of said processor, said units being connected to memory means (CA) containing program instructions to be executed and operands, at least one of said units being an addressing unit (EAD) for addressing said memory means (CA) to obtain the instructions and the operands, said processor being characterized in that said units (U1, U2, U3) include command block means (1) for decoding the instructions furnished by the memory means (CA) and autonomously executing functions defined by said instructions, each unit further including synchronizing means (15, 16, 17, 18, 19) for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit, said synchronizing means being adapted to interrupt (NOEX) said execution when:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result,

wherein said memory means (CA) includes interface means (ICU) connected to a first operand bus (OPE), and a second result bus (RES), said first and second buses serving respectively to read the operands and write the results into said memory means (CA);

each unit (U₁, U₂, U₃) being connected respectively via a first and second interface to said operand bus (OPE) and result bus (RES);

each unit (U1, U2, U3) includes including first means (3) for receiving and detecting a first indicator of ownership (OPE-OWN) associated with the operand bus (OPE) and first sending means (3a) for sending to the other units said first indicator of ownership (OPE-OWN);

each unit further including second means (3) for receiving and detecting a second indicator of ownership (RES-OWN) associated with the result bus (RES) and second sending means (3b) for sending to the other unit said second indicator of ownership (RES-OWN); and

said units are connected to one another via first and second control links (CD-OPE, CD-RES) respectively enabling the sending of said first and second indicators;

such that one of the conditions of effective reception of an operand by a unit is the detection by said unit of said first indicator (OPE-OWN); and

one of the conditions of effective sending of a result by a unit is the detection in said unit of said second indicator (RES-OWN),

wherein said memory means (CA) and said units (U₁, U₂, U₃) are connected to one another by availability links associated with the result bus (RES) and said units each including means for exchanging over these links availability signals (GET, EMPTY), such that another condition of effective sending of a result by a unit is the detection by said unit of an availability signal (GET, EMPTY) sent by the addressee of the results.

11. The processor of claim 5, wherein said units are connected to one another by links associated with the result bus (RES) notifying that a result has been sent for said units including owner unit means for exchanging result sending signals (RES-CP) and addressee signals (DEST) over said links, said result sending signals (RES-CP) and said addressee signals (DEST) being sent by the owner unit means when said owner unit means sends data over the result bus (RES) to the unit identified by said addressee signals (DEST);

and being characterized in that the condition of effective reception of a result by a unit is the detection of a result sending signal (RES-CP) and the coincidence of said addressee signals with the identity of said unit.

15. The processor of claim 5, wherein each unit includes a command block and the respective ownerships (OPE-OWN, RES-OWN) of the operand bus (OPE) and result bus (RES) at the beginning of execution of the microprogram of the instruction in progress are determined by the command block of each unit as a function of the operating code of said instructions;

and said ownerships being capable of modification during the execution of said microprogram by the owner unit means of said operand and result buses (OPE, RES).

22. The processor of claims 5, wherein each unit includes means (15, 19) for suspending execution of the microprogram in progress in each unit upon the detection of a conditional transfer of control microinstruction, the calculation of which is not performed by said unit, said units being connected to one another by an algorithm link (ALGO) enabling the unit that calculates the conditional transfer of control the transmit the results of said calculation to the other units, thus authorizing the continuation of the suspended microprograms in said other units.

28. The processor of claim 5, wherein said memory means (CA) comprise a cache memory, and said interface means (ICU) of said cache memory includes at least two independent buffers (OB1, OB2) connected at the input to the result bus (RES) and to the cache memory, and connected at the output to the operand bus (OPE) and to the cache memory.

36. The processor of claim 5, wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).

6. A processor for a data processing system including a plurality of microprogrammed processing units (U₁, U₂, U₃) sharing a set of functions of said processor, each unit being assigned the execution of a subset of functions of said processor, said units being connected to memory means (CA) containing program instructions to be executed and operands, at least one of said units being an addressing unit (EAD) for addressing said memory means (CA) to obtain the instructions and the operands, said processor being characterized in that said units (U₁, U₂, U₃) include command block means (1) for decoding the instructions furnished by the memory means (CA) and autonomously executing functions defined by said instructions, each unit further including synchronizing means (15, 16, 17, 18, 19) for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit, said synchronizing means being adapted to interrupt (NOEX) said execution when:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result;

wherein said memory means (CA) includes interface means (ICU) connected to a first operand bus (OPE), and a second result bus (RES), said first and second buses serving respectively to read the operands and write the results into said memory means (CA);

each unit (U₁, U₂, U₃) being connected respectively via a first and second interface to said operand bus (OPE) and result bus (RES);

each unit (U1, U2, U3) includes including first means (3) for receiving and detecting a first indicator of ownership (OPE-OWN) associated with the operand bus (OPE) and first sending means (3a) for sending to the other units said first indicator of ownership (OPE-OWN);

each unit further including second means (3) for receiving and detecting a second indicator of ownership (RES-OWN) associated with the result bus (RES) and second sending means (3b) for sending to the other unit said second indicator of ownership (RES-OWN); and

said units are connected to one another via first and second control links (CD-OPE, CD-RES) respectively enabling the sending of said first and second indicators;

such that one of the conditions of effective reception of an operand by a unit is the detection by said unit of said first indicator (OPE-OWN); and

one of the conditions of effective sending of a result by a unit is the detection in said unit of said second indicator (RES-OWN);

wherein said memory means (CA) are connected to said units via operand sending notification links associated with the operand bus (OPE) and include means for transmitting operand sending signals (SEND) over these links when said memory means send an operand, and each unit further including means (3) for receiving and detecting said operand sending signals, and being characterized in that another condition of effective reception of an operand by a unit is the detection by said unit of an expected sending signal (SEND), wherein said memory means (CA) and said units (U₁, U₂, U₃) are connected to one another by availability links associated with the result bus (RES), said units each including means for exchanging over these links availability signals (GET, EMPTY) such that another condition of effective sending of a result by a unit is the detection by said unit of an availability signal (GET, EMPTY) sent by the addressee of the result;

wherein said memory means (CA) and said units (U₁, U₂, U₃) are connected to one another by availability links associated with the result bus (RES), said units each including means for exchanging over these links availability signals (GET, EMPTY), such that another condition of effective sending of a result by a unit is the detection by said unit of an availability signal (GET, EMPTY) sent by the addressee of the result.

16. The processor of claim 6, wherein each unit includes a command block and the respective ownerships (OPE-OWN, RES-OWN) of the operand bus (OPE) and result bus (RES) at the beginning of execution of the microprogram of the instruction in progress are determined by the command block of each unit as a function of the operating code of said instructions;

and said ownerships being capable of modification during the execution of said microprogram by the owner unit means of said operand and result buses (OPE, RES).

7. A processor for a data processing system including a plurality of microprogrammed processing units (U₁, U₂, U₃) sharing a set of functions of said processor, each unit being assigned the execution of a subset of functions of said processor, said units being connected to memory means (CA) containing program instructions to be executed and operands, at least one of said units being an addressing unit (EAD) for addressing said memory means (CA) to obtain the instructions and the operands, said processor being characterized in that said units (U1, U2, U3) include command block means (1) for decoding the instructions furnished by the memory means (CA) and autonomously executing functions defined by said instructions, each unit further including synchronizing means (15, 16, 17, 18, 19) for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit, said synchronizing means being adapted to interrupt (NOEX) said execution when:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result;

wherein said memory means (CA) includes interface means (ICU) connected to a first operand bus (OPE), and a second result bus (RES), said first and second buses serving respectively to read the operands and write the results into said memory means (CA);

each unit (U₁, U₂, U₃) being connected respectively via a first and second interface to said operand bus (OPE) and result bus (RES);

each unit (U1, U2, U3) includes including first means (3) for receiving and detecting a first indicator of ownership (OPE-OWN) associated with the operand bus (OPE) and first sending means (3a) for sending to the other units said first indicator of ownership (OPE-OWN);

each unit further including second means (3) for receiving and detecting a second indicator of ownership (RES-OWN) associated with the result bus (RES) and second sending means (3b) for sending to the other unit said second indicator of ownership (RES-OWN); and

said units are connected to one another via first and second control links (CD-OPE, CD-RES) respectively enabling the sending of said first and second indicators;

such that one of the conditions of effective reception of an operand by a unit is the detection by said unit of said first indicator (OPE-OWN); and

one of the conditions of effective sending of a result by a unit is the detection in said unit of said second indicator (RES-OWN);

wherein said memory means (CA) are connected to said units via operand sending notification links associated with the operand bus (OPE) and include means for transmitting operand sending signals (SEND) over these links when said memory means send an operand, and each unit further including means (3) for receiving and detecting said operand sending signals, and being characterized in that another condition of effective reception of an operand by a unit is the detection by said unit of an expected sending signal (SEND);

wherein said units are connected to said memory means (CA) via reception acknowledgement links associated with the operand bus (OPE), and each unit including means (3) for sending over said reception acknowledgement links a signal of reception acknowledgement (GOT) when an operand is effectively received by said unit in such a way as to inform said memory means (CA) of the receipt of the operand;

wherein said memory means (CA) and said units (U₁, U₂, U₃) are connected to one another by availability links associated with the result bus (RES), said units each including means for exchanging over these links availability signals (GET, EMPTY), such that another condition of effective sending of a result by a unit is the detection by said unit of an availability signal (GET, EMPTY) sent by the addressee of the result.

17. The processor of claim 7, wherein each unit includes a command block and the respective ownerships (OPE-OWN, RES-OWN) of the operand bus (OPE) and result bus (RES) at the beginning of execution of the microprogram of the instruction in progress are determined by the command block of each unit as a function of the operating code of said instructions;

and said ownerships being capable of modification during the execution of said microprogram by the owner unit means of said operand and result buses (OPE, RES).

9. A processor for a data processing system including a plurality of microprogrammed processing units (U₁, U₂, U₃) sharing a set of functions of said processor, each unit being assigned the execution of a subset of functions of said processor, said units being connected to memory means (CA) containing program instructions to be executed and operands, at least one of said units being an addressing unit (EAD) for addressing said memory means (CA) to obtain the instructions and the operands, said processor being characterized in that said units (U1, U2, U3) include command block means (1) for decoding the instructions furnished by the memory means (CA) and autonomously executing functions defined by said instructions, each unit further including synchronizing means (15, 16, 17, 18, 19) for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit, said synchronizing means being adapted to interrupt (NOEX) said execution when:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result;

wherein said memory means (CA) includes interface means (ICU) connected to a first operand bus (OPE), and a second result bus (RES), said first and second buses serving respectively to read the operands and write the results into said memory means (CA);

each unit (U₁, U₂, U₃) being connected respectively via a first and second interface to said operand bus (OPE) and result bus (RES);

each unit (U1, U2, U3) includes including first means (3) for receiving and detecting a first indicator of ownership (OPE-OWN) associated with the operand bus (OPE) and first sending means (3a) for sending to the other units said first indicator of ownership (OPE-OWN);

each unit further including second means (3) for receiving and detecting a second indicator of ownership (RES-OWN) associated with the result bus (RES) and second sending means (3b) for sending to the other unit said second indicator of ownership (RES-OWN); and

said units are connected to one another via first and second control links (CD-OPE, CD-RES) respectively enabling the sending of said first and second indicators;

such that one of the conditions of effective reception of an operand by a unit is the detection by said unit of said first indicator (OPE-OWN); and

one of the conditions of effective sending of a result by a unit is the detection in said unit of said second indicator (RES-OWN);

wherein said memory means (CA) are connected to said units via operand sending notification links associated with the operand bus (OPE) and include means for transmitting operand sending signals (SEND) over these links when said memory means send an operand, and each unit further including means (3) for receiving and detecting said operand sending signals, and being characterized in that another condition of effective reception of an operand by a unit is the detection by said unit of an expected sending signal (SEND);

wherein said units are connected to one another by links associated with the result bus (RES) notifying that a result has been sent for said units including owner unit means for exchanging result sending signals (RES-CP) and addressee signals (DEST) over said links, said result sending signals (RES-CP) and said addressee signals (DEST) being sent by the owner unit means when said owner unit means sends data over the result bus (RES) to the unit identified by said addressee signals (DEST); and

being characterized in that the condition of effective reception of a result by a unit is the detection of a result sending signal (RES-CP) and the coincidence of said addressee signals with the identify of said unit.

18. A processor for a data processing system including a plurality of microprogrammed processing units (U₁, U₂, U₃) sharing a set of functions of said processor, each unit being assigned the execution of a subset of functions of said processor, said units being connected to memory means (CA) containing program instructions to be executed and operands, at least one of said units being an addressing unit (EAD) for addressing said memory means (CA) to obtain the instructions and the operands, said processor being characterized in that said units (U1, U2, U3) include command block means (1) for decoding the instructions furnished by the memory means (CA) and autonomously executing functions defined by said instructions, each unit further including synchronizing means (15, 16, 17, 18, 19) for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit, said synchronizing means being adapted to interrupt (NOEX) said execution when:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result;

wherein said memory means (CA) includes interface means (ICU) connected to a first operand bus (OPE), and a second result bus (RES), said first and second buses serving respectively to read the operands and write the results into said memory means (CA);

each unit (U₁, U₂, U₃) being connected respectively via a first and second interface to said operand bus (OPE) and result bus (RES);

each unit (U1, U2, U3) includes including first means (3) for receiving and detecting a first indicator of ownership (OPE-OWN) associated with the operand bus (OPE) and first sending means (3a) for sending to the other units said first indicator of ownership (OPE-OWN);

each unit further including second means (3) for receiving and detecting a second indicator of ownership (RES-OWN) associated with the result bus (RES) and second sending means (3b) for sending to the other unit said second indicator of ownership (RES-OWN); and

said units are connected to one another via first and second control links (CD-OPE, CD-RES) respectively enabling the sending of said first and second indicators;

such that one of the conditions of effective reception of an operand by a unit is the detection by said unit of said first indicator (OPE-OWN); and

one of the conditions of effective sending of a result by a unit is the detection in said unit of said second indicator (RES-OWN);

wherein said units are connected to one another by links associated with the result bus (RES) for notifying that a result has been sent, said units including owner unit means for exchanging result sending signals (RES-CP) and addressee signals (DEST) over said links, said result sending signals (RES-CP) and said addressee signals (DEST) being sent by the owner unit means when said owner unit means sends data over the result bus (RES) to the unit identified by said addressee signals (DEST); and

being characterized in that the condition of effective reception of a result by a unit is the detection of a result sending signal (RES-CP) and the coincidence of said addressee signals with the identity of said unit, and

wherein each unit includes a command block and the respective ownerships (OPE-OWN, RES-OWN) of the operand bus (OPE) and result bus (RES) at the beginning of execution of the microprogram of the instruction in progress are determined by the command block of each unit as a function of the operating code of said instructions; and

said ownerships being capable of modification during the execution of said microprogram by the owner unit means of said operand and result buses (OPE, RES).

31. A processor for a data processing system including a plurality of microprogrammed processing units (U₁, U₂, U₃) sharing a set of functions of said processor, each unit being assigned the execution of a subset of functions of said processor, said units being connected to memory means (CA) containing program instructions to be executed and operands, at least one of said units being an addressing unit (EAD) for addressing said memory means (CA) to obtain the instructions and the operands, said processor being characterized in that said units (U1, U2, U3) include command block means (1) for decoding the instructions furnished by the memory means (CA) and autonomously executing functions defined by said instructions, each unit further including synchronizing means (15, 16, 17, 18, 19) for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit, said synchronizing means being adapted to interrupt (NOEX) said execution when:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result;

wherein said memory means (CA) includes interface means (ICU) connected to a first operand bus (OPE), and a second result bus (RES), said first and second buses serving respectively to read the operands and write the results into said memory means (CA);

each unit (U₁ U₂, U₃) being connected respectively via a first and second interface to said operand bus (OPE) and result bus (RES);

each unit (U1, U2, U3) includes including first means (3) for receiving and detecting a first indicator of ownership (OPE-OWN) associated with the operand bus (OPE) and first sending means (3a) for sending to the other units said first indicator of ownership (OPE-OWN);

each unit further including second means (3) for receiving and detecting a second indicator of ownership (RES-OWN) associated with the result bus (RES) and second sending means (3b) for sending to the other unit said second indicator of ownership (RES-OWN); and

said units are connected to one another via first and second control links (CD-OPE, CD-RES) respectively enabling the sending of said first and second indicators;

such that one of the conditions of effective reception of an operand by a unit is the detection by said unit of said first indicator (OPE-OWN); and

one of the conditions of effective sending of a result by a unit is the detection in said unit of said second indicator (RES-OWN);

wherein each unit includes means (15,

     19) for suspending execution of the microprogram in progress in each unit upon the detection of a conditional transfer of control microinstruction, the calculation of which is not performed by said unit, said units being connected to one another by an algorithm link (ALGO) enabling the unit that calculates the conditional transfer of control to transmit the results of said calculation to the other units, thus authorizing the continuation of the suspended microprograms in said other units; and

wherein said memory means (CA) comprise a cache memory, and said interface means (ICU) of said cache memory includes at least two independent buffers (OB1, OB2) connected at the input to the result bus (RES) and to the cache memory, and connected at the output to the operand bus (OPE) and to the cache memory.

40. A processor for a data processing system including a plurality of microprogrammed processing units (U₁, U₂, U₃) sharing a set of functions of said processor, each unit being assigned the execution of a subset of functions of said processor, said units being connected to memory means (CA) containing program instructions to be executed and operands, at least one of said units being an addressing unit (EAD) for addressing said memory means (CA) to obtain the instructions and the operands, said processor being characterized in that said units (U1, U2, U3) include command block means (1) for decoding the instructions furnished by the memory means (CA) and autonomously executing functions defined by said instructions, each unit further including synchronizing means (15, 16, 17, 18, 19) for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit, said synchronizing means being adapted to interrupt (NOEX) said execution when:

either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,

or a result expected by said unit and calculated by another unit is not effectively received by said unit,

or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result;

wherein said memory means (CA) includes interface means (ICU) connected to a first operand bus (OPE), and a second result bus (RES), said first and second buses serving respectively to read the operands and write the results into said memory means (CA);

each unit (U₁, U₂, U₃) being connected respectively via a first and second interface to said operand bus (OPE) and result bus (RES);

each unit (U1, U2, U3) includes including first means (3) for receiving and detecting a first indicator of ownership (OPE-OWN) associated with the operand bus (OPE) and first sending means (3a) for sending to the other units said first indicator of ownership (OPE-OWN);

each unit further including second means (3) for receiving and detecting a second indicator of ownership (RES-OWN) associated with the result bus (RES) and second sending means (3b) for sending to the other unit said second indicator of ownership (RES-OWN); and

said units are connected to one another via first and second control links (CD-OPE, CD-RES) respectively enabling the sending of said first and second indicators;

such that one of the conditions of effective reception of an operand by a unit is the detection by said unit of said first indicator (OPE-OWN); and

one of the conditions of effective sending of a result by a unit is the detection in said unit of said second indicator (RES-OWN);

wherein said memory means (CA) comprise a cache memory, and said interface means (ICU) of said cache memory includes at least two independent buffers (OB1, OB2) connected at the input to the result bus (RES) and to the cache memory, and connected at the output to the operand bus (OPE) and to the cache memory; and

wherein said processing units, in addition to the addressing unit (EAD), include binary and a decimal calculation unit (BDP) and a floating point calculation unit (FPP).