Semi-conductor integrated circuit device including connection and disconnection mechanisms to connect and disconnect monitor circuit and semiconductor integrated circuit from each other

• US 5,410,163 A
• Filed: 08/29/1994
• Issued: 04/25/1995
• Est. Priority Date: 03/18/1992
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Murakami, Shizuhiko
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/296,587
• Time in Patent Office: 239 Days
• Field of Search: 257/665, 257/50, 257/529, 257/530, 257/148, 257/48
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A monitor circuit provided in a chip in which a semiconductor integrated circuit is formed. Connection mechanisms and disconnection mechanisms are connected in series in wirings connected to the monitor circuit. Before using the semiconductor integrated circuit, in the state that the connection mechanisms are opened, the monitor circuit is tested without conducting the monitor circuit to the semiconductor integrated circuit. In the case of using the semiconductor integrated circuit, the connection mechanisms are written to close them, so that the monitor circuit is connected to the semiconductor circuit main body and is thus driven. Further, after using the semiconductor integrated circuit, the monitor circuit is separated from the semiconductor integrated circuit by writing the disconnection mechanisms, to be investigated for the characteristic.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor integrated circuit main body having a circuit to be monitored;

a monitor circuit to monitor said circuit to be monitored, provided on a chip in which said semiconductor integrated circuit main body is also mounted, said monitor circuit having the same structure as that of said circuit to be monitored;

wirings extending from said monitor circuit to the semiconductor integrated circuit main body;

connection mechanisms connected in series with said monitor circuit and said semiconductor integrated circuit main body through said wirings to disconnect said monitor circuit from said semiconductor integrated circuit main body through said wirings during an initial test state of said monitor circuit and to connect said monitor circuit to said semiconductor integrated circuit main body through said wirings during an operation state of said semiconductor integrated circuit main body so that said monitor circuit and said circuit to be monitored operate under the same operational condition; and

disconnection mechanisms connected in series with said monitor circuit and said semiconductor integrated circuit main body through said wirings to connect said monitor circuit with said semiconductor integrated circuit main body through said wirings during the operation state of said semiconductor integrated circuit main body so that said monitor circuit and said circuit to be monitored operate under the same operational condition and to disconnect said monitor circuit from said semiconductor integrated circuit main body through said wirings during a second test state of said monitor circuit after completion of the operation state.

2. A semiconductor integrated circuit device according to claim 1, wherein said wirings are connected to power supply wirings and said semiconductor integrated circuit main body.

3. A semiconductor integrated circuit device according to claim 1, further comprising electrode pads, each said electrode pad being led from a terminal, on a side near said monitor circuit, of each of said disconnection mechanisms.

4. A semiconductor integrated circuit device according to claim 3, wherein each said electrode pad is led from the terminal, on the side near said monitor circuit, of each of terminals of said disconnection mechanisms and said connection mechanisms.

5. A semiconductor integrated circuit device according to claim 1, wherein each of said connection mechanisms comprises a dielectric breakdown type semiconductor device.

6. A semiconductor integrated circuit device according to claim 1, wherein each of said disconnection mechanisms comprises a fuse of semiconductor.

7. A semiconductor integrated circuit device according to claim 1, wherein said monitor circuit includes a field effect transistor.

8. A semiconductor integrated circuit device according to claim 1, wherein said monitor circuit includes a complementary field effect transistor circuit.

9. A semiconductor integrated circuit device according to claim 1, wherein said monitor circuit includes a bipolar transistor.

10. A semiconductor integrated circuit device according to claim 1, wherein said monitor circuit includes a diode.

11. A semiconductor integrated circuit device according to claim 1, wherein each of said connection mechanisms comprises a pn-junction breakdown type semiconductor device.