Dynamic random access memory having bit lines buried in semiconductor substrate

• US 5,410,169 A
• Filed: 02/22/1993
• Issued: 04/25/1995
• Est. Priority Date: 02/26/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamamoto, Tadashi, Sawada, Shizuo
• Primary Examiner(s): LARKINS, WILLIAM
• Application Number:
  US08/020,444
• Time in Patent Office: 792 Days
• Field of Search: 357/23.6, 257/621, 257/305, 257/296, 257/301, 257/306
• US Class Current: 257/301
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

There is provided a DRAM memory cell structure. The semiconductor structure includes a semiconductor substrate of a first conductivity type having a main surface, source and drain regions of a second conductivity type formed in the main surface area of the semiconductor substrate, word lines extending in a first plane direction and formed on those portions of the semiconductor substrate which respectively lie between the source and drain regions, capacitors each having one of the source and drain regions as a storage node electrode, and bit lines buried in the semiconductor substrate and electrically connected to the source or drain regions, respectively.

Claims

1. A semiconductor memory device, comprising:

a semiconductor body of a first conductivity type having first and second spaced-apart parallel grooves which extend in a first direction formed therein, said first and second grooves defining a middle region therebetween;

first and second field insulating films formed on the surface of said middle region, each of said first and second field insulating films extending so as to contact both said first and second grooves;

first and second spaced-apart parallel word lines extending in a second direction perpendicular to the first direction;

a first semiconductor region of a second conductivity type formed in a first portion of said middle region, said first portion of said middle region being disposed between one of said first and second words lines and one of said first and second field insulating films, and said first semiconductor region serving as a source of a first memory cell and being connected to a first memory capacitor;

a second semiconductor region of the second conductivity type formed in a second portion of said middle region, said second portion of said middle region being disposed between the other of said first and second word lines and the other of said first and second field insulating films, and said second semiconductor region serving as a source of a second memory cell and being connected to a second memory capacitor;

a third semiconductor region of the second conductivity type formed in a third portion of said middle region, said third portion of said middle region being disposed between said first and second word lines and serving as a drain which is common to said first and second memory cells;

a first insulating film formed on an exposed surface of said first groove and having an opening therein which extends to said third semiconductor region;

a second insulating film formed on an exposed surface of said second groove;

a first bit line formed in said first groove, said first bit line being connected to said third semiconductor region via an electrical path which extends through said opening in a direction substantially perpendicular to a direction of current paths between said sources of the first and second memory cells and said common drain; and

a second bit line formed in said second groove.

2. A semiconductor memory device according to claim 1, wherein said first and second grooves provide element isolation in the second direction.

3. A semiconductor memory device according to claim 2, wherein said first memory capacitor comprises a storage node electrode connected to said first semiconductor region and said second memory capacitor comprises a storage node electrode connected to said second semiconductor region.

4. A semiconductor memory device according to claim 3, wherein each of said first and second memory capacitors is a stacked-type memory capacitor, and wherein said first and second memory capacitors further comprise:

a plate electrode formed on an entire surface of said semiconductor body.

5. A semiconductor memory device according to claim 3, wherein said storage node electrodes of said first and second memory capacitors overlap said first and second grooves.

6. A semiconductor memory device according to claim 5, wherein each of said first and second memory capacitors is a stacked-type memory capacitor, and wherein said first and second memory capacitors further comprise:

a plate electrode formed on an entire surface of said semiconductor body.

7. A semiconductor memory device according to claim 4, wherein said first and second bit lines are composed of phosphorus-doped polysilicon.

8. A semiconductor memory device, comprising:

a semiconductor body having a major surface;

first and second grooves in said major surface of said semiconductor body;

first and second field insulating film portions on said major surface of said semiconductor body between said first and second grooves, said first and second field insulating film portions extending to said first and second grooves to define an active region surrounded by said first and second grooves and said first and second field insulating film portions;

source and drain regions in said active region, wherein a junction between said source region and said semiconductor body extends to both said first and second grooves and a junction between said drain region and said semiconductor body extends to both said first and second grooves;

a gate electrode insulatively arranged on a channel region between said source and drain regions;

a first insulating film on portions of said semiconductor body exposed by said first and second grooves;

a first conductive film on said first insulating film and filling in said grooves to define first and second bit lines; and

connecting means for electrically connecting one of said first and second bit lines to a first one of said source and drain regions.

9. A semiconductor memory device according to claim 8, wherein said connecting means comprises:

an opening in said first insulating film adjacent to said first one of said source and drain regions; and

a diffusion region contacting said one of said first and second bit lines and said first one of said source and drain regions and extending through said opening.

10. A semiconductor memory device according to claim 8, wherein said connecting means comprises:

a second conductive film contacting an upper surface of said first one of said source and drain regions and an upper surface of said one of said first and second bit lines.

11. A semiconductor memory device according to claim 10, wherein said second conductive film is a phosphorous-doped polysilicon layer.

12. A semiconductor memory device according to claim 8, further comprising:

a capacitor having a storage node contact electrode connected to a second one of said source and drain regions.

13. A semiconductor memory device according to claim 12, further comprising:

a trench in said active region,

wherein said storage node contact electrode of said capacitor comprises a second conductive film on a portion of said semiconductor body exposed by said trench.

14. A semiconductor memory device according to claim 13, wherein said capacitor further comprises:

a dielectric layer on said storage node contact electrode; and

a third conductive film on said dielectric layer and filling in said trench to define a plate electrode.

15. A semiconductor memory device according to claim 12, further comprising a trench in said active region and wherein said capacitor comprises:

a second insulating film on portions of said semiconductor body exposed by said trench;

a third conductive film on said second insulating film and filling in said trench to define said storage node contact electrode; and

wherein said semiconductor body comprises a plate electrode.